Package: yosys
Version: 0.65-1
Architecture: amd64
Maintainer: Ubuntu Developers <ubuntu-devel-discuss@lists.ubuntu.com>
Original-Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Installed-Size: 26486
Depends: libc6 (>= 2.43), libffi8 (>= 3.4), libgcc-s1 (>= 3.3.1), libreadline8t64 (>= 6.0), libstdc++6 (>= 14), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0), python3:any, python3-click, yosys-abc (>= 0.32-1)
Recommends: xdot
Section: electronics
Priority: optional
Homepage: https://github.com/YosysHQ/yosys
Description: Framework for Verilog RTL synthesis
 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
