Package: yosys-abc
Source: yosys
Version: 0.66-1
Architecture: amd64
Maintainer: Ubuntu Developers <ubuntu-devel-discuss@lists.ubuntu.com>
Original-Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Installed-Size: 14914
Depends: libbz2-1.0, libc6 (>= 2.38), libgcc-s1 (>= 3.4), libreadline8t64 (>= 6.0), libstdc++6 (>= 13.1), zlib1g (>= 1:1.1.4)
Breaks: yosys (<< 0.32-1)
Replaces: yosys (<< 0.32-1)
Section: electronics
Priority: optional
Homepage: https://github.com/YosysHQ/yosys
Description: Sequential Logic Synthesis and Verification Algorithms
 ABC is a system for synthesis and verification of binary sequential logic
 circuits appearing in synchronous hardware designs. It combines scalable
 logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
 DAG-based technology mapping for look-up tables and standard cells, and
 innovative algorithms for sequential synthesis and verification.
 .
 This is a fork of berkeley-abc maintained by the YosysHQ team for use in
 the yosys RTL synthesis framework.
