Package: yosys-plugin-ghdl
Version: 0.0~git20230419.5b64ccf-6
Architecture: amd64
Maintainer: Ubuntu Developers <ubuntu-devel-discuss@lists.ubuntu.com>
Original-Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Installed-Size: 247
Depends: libc6 (>= 2.14), libgcc-s1 (>= 3.3.1), libghdl-5-0-1 (>= 5.0.1+dfsg), libstdc++6 (>= 13.1), ghdl-mcode (>= 3.0.0) | ghdl-gcc
Section: electronics
Priority: optional
Homepage: https://github.com/ghdl/ghdl-yosys-plugin
Description: VHDL to RTL synthesis plugin using GHDL
 This yosys plugin allows running RTL synthesis from VHDL source code
 instead of yosys' native Verilog.
 .
 This allows a full synthesis flow from VHDL to hardware for FPGAs where
 the GHDL compiler is used to analyse the VHDL sources and yosys is used to
 perform logic optimization, technology mapping and convertion to netlist
 format.
