v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=CONNECTOR_4
template="device=CONNECTOR_4 name=CONN? class=IO pins=4 "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {@name} 0 -140 2 1 0.333333 0.333333 {}

L 4 0 0 50 0 {}
L 4 50 -130 50 0 {}
L 4 0 -130 50 -130 {}
L 4 0 -130 0 0 {}

L 4 50 -80 140 -80 {}
L 4 50 -50 140 -50 {}
L 4 50 -20 140 -20 {}
L 4 50 -110 140 -110 {}






L 3 140 -110 170 -110 {}
B 5 167.5 -112.5 172.5 -107.5 {pinnumber=1
pinseq=1
name=1
dir=inout
}
T {@#0:pinnumber} 25 -105 2 1 0.266667 0.266667 {layer=13}
L 3 140 -80 170 -80 {}
B 5 167.5 -82.5 172.5 -77.5 {pinnumber=2
pinseq=2
name=2
dir=inout
}
T {@#1:pinnumber} 25 -75 2 1 0.266667 0.266667 {layer=13}
L 3 140 -50 170 -50 {}
B 5 167.5 -52.5 172.5 -47.5 {pinnumber=3
pinseq=3
name=3
dir=inout
}
T {@#2:pinnumber} 25 -45 2 1 0.266667 0.266667 {layer=13}
L 3 140 -20 170 -20 {}
B 5 167.5 -22.5 172.5 -17.5 {pinnumber=4
pinseq=4
name=4
dir=inout
}
T {@#3:pinnumber} 25 -15 2 1 0.266667 0.266667 {layer=13}
