v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
verilog_primitive=true
vhdl_primitive=true
vhdl_format="@@Y <= @@A after 90 ps;"
verilog_format="assign #90 @@Y = ~@@A ;"
format="@name @pinlist @symname ROUT=@ROUT"
template="name=x1 ROUT=1000"
}
V {}
S {}
E {}
L 4 -40 0 -20 0 {}
L 4 -20 -20 20 0 {}
L 4 -20 -20 -20 20 {}
L 4 -20 20 20 0 {}
L 4 30 -0 40 -0 {}
B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out }
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in }
A 4 25 -0 5 180 360 {}
T {@symname} -47.5 24 0 0 0.3 0.3 {}
T {@name} 25 -22 0 0 0.2 0.2 {}
T {Y} 7.5 -6.5 0 1 0.2 0.2 {}
T {A} -17.5 -6.5 0 0 0.2 0.2 {}
T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {}
T {@#1:net_name} -22.5 6.25 0 1 0.15 0.15 {layer=15}
T {@#0:net_name} 17.5 6.25 0 0 0.15 0.15 {layer=15}
