v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=spice-subcircuit-LL
template="device=spice-subcircuit-LL name=A? model-name=unknown "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {@name} 10 -50 0 0 0.333333 0.333333 { vcenter=true}
T {SPICE .SUBCKT} 60 -50 0 0 0.333333 0.333333 { vcenter=true}
T {@model-name} 10 -20 0 0 0.333333 0.333333 {}

L 4 0 -30 220 -30 {}
L 4 220 -70 220 -30 {}
L 4 0 -70 220 -70 {}
L 4 0 -70 0 -30 {}







