v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -20 130 -20 {}
L 4 -130 20 130 20 {}
L 4 -130 -20 -130 20 {}
L 4 130 -20 130 20 {}
L 4 -150 -10 -130 -10 {}
L 4 130 -10 150 -10 {}
L 4 -150 10 -130 10 {}
B 5 -152.5 -12.5 -147.5 -7.5 {name=LDPRECH dir=in }
B 5 147.5 -12.5 152.5 -7.5 {name=LDBL dir=inout }
B 5 -152.5 7.5 -147.5 12.5 {name=vss dir=in }
T {@symname} -63 -6 0 0 0.3 0.3 {}
T {@name} 135 -32 0 0 0.2 0.2 {}
T {LDPRECH} -125 -14 0 0 0.2 0.2 {}
T {LDBL} 125 -14 0 1 0.2 0.2 {}
T {vss} -125 6 0 0 0.2 0.2 {}
