v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=gate
vhdl_stop=true
verilog_format = "assign #@del @@Y = ~ @@A[max:0] ;"
vhdl_format = " @@Y <= not @@A[max:0] after @del ps ;"
format="@name [ @@A[max:0]  ] @@Y inv"
template="name=x1 delay=\\"70 ps\\" del=70"
generic_type="delay=time"
}
V {}
S {}
E {}
L 4 -40 0 -25 0 {}
L 4 -25 -20 -25 20 {}
L 4 -25 -20 15 0 {}
L 4 -25 20 15 0 {}
L 4 25 0 40 0 {}
B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out verilog_type=wire}
B 5 -42.5 -2.5 -37.5 2.5 {name=A[max:0] dir=in}
A 4 20 0 5 180 360 {}
T {@name} -23.75 -5 0 0 0.2 0.2 {}
T {IV} -2.8125 -28.75 0 0 0.3 0.3 {}
