v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=NPN_TRANSISTOR
template="device=NPN_TRANSISTOR name=Q? "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {@name} 90 -50 2 1 0.333333 0.333333 {}
T {Generic_Transistor} 90 -30 2 1 0.333333 0.333333 {}


L 4 40 -40 60 -20 {}
L 4 40 -60 60 -80 {}
L 4 40 -70 40 -30 {}
L 4 18.4 -50 40 -50 {}
L 4 56.4 -27.2 60 -20 {}
L 4 52.8 -23.6 60 -20 {}
L 4 52.8 -23.6 56.4 -27.2 {}

A 4 50 -50.1 31.6 0 360 {}





L 3 60 -100 60 -80 {}
B 5 57.5 -102.5 62.5 -97.5 {pinnumber=3
pinseq=1
name=3
dir=inout
}
T {@#0:pinnumber} 50 -85 2 1 0.2 0.2 {layer=13}
L 3 0 -50 18.4 -50 {}
B 5 -2.5 -52.5 2.5 -47.5 {pinnumber=2
pinseq=2
name=2
dir=inout
}
T {@#1:pinnumber} 10 -55 2 1 0.2 0.2 {layer=13}
L 3 60 -20 60 0 {}
B 5 57.5 -2.5 62.5 2.5 {pinnumber=1
pinseq=3
name=1
dir=inout
}
T {@#2:pinnumber} 50 -5 2 1 0.2 0.2 {layer=13}
