v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
format="@name @pinlist @symname ROUT=@ROUT"
template="name=x1 ROUT=1000"}
V {}
S {}
E {}
L 4 -40 -20 -20 -20 {}
L 4 35 0 60 0 {}
L 4 -20 -30 -20 30 {}
L 4 -20 -30 5 -30 {}
L 4 -20 30 5 30 {}
L 4 -40 0 -20 0 {}
L 4 -40 20 -20 20 {}
B 5 57.5 -2.5 62.5 2.5 {name=Y dir=out verilog_type=wire}
B 5 -42.5 -22.5 -37.5 -17.5 {name=A dir=in}
B 5 -42.5 -2.5 -37.5 2.5 {name=B dir=in}
B 5 -42.5 17.5 -37.5 22.5 {name=C dir=in}
A 4 5 0 30 270 180 {}
T {@name} -16.25 -5 0 0 0.2 0.2 {}
T {@#1:net_name} -22.5 -17.5 0 1 0.15 0.15 {layer=15}
T {@#0:net_name} 35 1.25 0 0 0.15 0.15 {layer=15}
T {@#2:net_name} -22.5 2.5 0 1 0.15 0.15 {layer=15}
T {@#3:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15}
