v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=inv
vhdl_stop=true
format="#@spiceprefix\\\\MA#@name @#0 @#1 @VCCPIN @VCCBPIN @modelp w=@wp l=@lp m=@m
#@spiceprefix\\\\MB#@name @#0 @#1 @VSSPIN @VSSBPIN @modeln w=@wn l=@ln m=@m"
template="name=x1 m=1 
+ wn=1 ln=0.2 modeln=nmos
+ wp=2 lp=0.2 modelp=pmos
+ VCCPIN=VCC VCCBPIN=VCC VSSPIN=VSS VSSBPIN=VSS"
extra="VCCPIN VCCBPIN VSSPIN VSSBPIN"
generic_type="m=integer 
wn=real ln=real 
wp=real lp=real 
VCCPIN=string 
VCCBPIN=string
VSSPIN=string 
VSSBPIN=string
modeln=string
modelp=string"

verilog_stop=true
}
V {}
S {}
E {}
L 4 -40 0 -25 0 {}
L 4 -25 -20 -25 20 {}
L 4 -25 -20 15 0 {}
L 4 -25 20 15 0 {}
L 4 25 0 40 0 {}
B 5 37.5 -2.5 42.5 2.5 {name=Z dir=out verilog_type=wire}
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in}
A 4 20 0 5 180 360 {}
T {@name
@wn\\/@ln
@modeln} -20 60 2 1 0.2 0.2 {}
T {m=@m
@wp\\/@lp
@modelp} -20 -60 0 0 0.2 0.2 {}
T {@VCCPIN} 10 -20 0 0 0.2 0.2 {}
