v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=7414
template="slot=1 numslots=6 device=7414 name=U? pins=14 "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {@device} 30 0 2 1 0.333333 0.333333 {}
T {@name} 80 -80 2 1 0.333333 0.333333 {}


L 4 30 -80 30 -20 {}
L 4 30 -80 80 -50 {}
L 4 30 -20 80 -50 {}
L 4 39 -56 39 -36 {}
L 4 39 -36 45 -40 {}
L 4 39 -56 45 -60 {}
L 4 33 -32 39 -36 {}
L 4 45 -60 45 -40 {}
L 4 45 -60 52 -64 {}

A 4 85 -50 5 0 360 {}





L 3 0 -50 30 -50 {}
B 5 -2.5 -52.5 2.5 -47.5 {
pinseq=1
name=1
dir=inout
pinnumber=1:3:5:9:11:13
}
T {@#0:pinnumber} 10 -60 2 1 0.333333 0.333333 {layer=13}
L 3 90 -50 120 -50 {}
B 5 117.5 -52.5 122.5 -47.5 {
pinseq=2
name=2
dir=inout
pinnumber=2:4:6:8:10:12
}
T {@#1:pinnumber} 100 -60 2 1 0.333333 0.333333 {layer=13}
