v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
V {}
S {}
E {}
N 370 -360 370 -300 {lab=LDBL}
N 370 -440 370 -420 {lab=vss}
C {iopin.sym} 600 -180 0 0 {name=p1 lab=LDBL}
C {lab_pin.sym} 330 -390 0 0 {name=p711 lab=LDPRECH}
C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"}
C {lab_pin.sym} 370 -300 0 0 {name=p5 lab=LDBL}
C {lab_pin.sym} 370 -440 0 0 {name=p2 lab=vss}
C {nlv.sym} 350 -390 0 0 {name=m0 model=cmosn w=6u l=2.4u m=1
}
C {ipin.sym} 430 -200 0 0 {name=p6 lab=LDPRECH}
C {ipin.sym} 430 -160 0 0 {name=p7 lab=vss}
