v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=ao21
vhdl_stop=true
verilog_stop=true
verilog_format="and #aa#@name ( #xx#@name , @@A , @@B );
nor #(@risedel , @falldel ) #bb#@name (@@Z , #xx#@name , @@C );" 
format="@name @pinlist @symname"
template="name=x1 risedel=100 falldel=100"
}
V {}
S {}
E {}
L 4 -109.6875 20 -22.65625 20 {}
L 4 45 0 60 0 {}
L 4 -25 30 -5 30 {}
L 4 -25 -30 -5 -30 {}
L 4 -110 -20 -95 -20 {}
L 4 -110 -60 -95 -60 {}
L 4 -95 -65 -95 -15 {}
L 4 -95 -15 -70 -15 {}
L 4 -95 -65 -70 -65 {}
L 4 -45 -40 -35 -40 {}
L 4 -35 -40 -35 -20 {}
L 4 -35 -20 -22.5 -20 {}
B 5 57.5 -2.5 62.5 2.5 {name=Z dir=out verilog_type=wire}
B 5 -112.5 -62.5 -107.5 -57.5 {name=A dir=in}
B 5 -112.5 -22.5 -107.5 -17.5 {name=B dir=in}
B 5 -112.5 17.5 -107.5 22.5 {name=C dir=in}
A 4 40 0 5 180 360 {}
A 4 -9.64285714285711 17.85714285714289 48.0818286351295 21.80140948635181 62.65738573560834 {}
A 4 -4.6875 -11.25 41.25118369513777 269.5659493678606 74.60789655596687 {}
A 4 -112.5 0 92.5 341.0753555839487 37.8492888321025 {}
A 4 -70 -40 25 270 180 {}
T {@name} -16.25 5 0 0 0.2 0.2 {}
T {AO21} -17.5 -16.25 0 0 0.3 0.3 {}
