v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=npn
format="@name @pinlist  @symname @area"
template="name=q1 area=1"}
V {}
S {}
E {}
L 4 0 -30 0 30 {}
L 4 -20 0 -12.5 0 {}
L 4 -20 0 0 0 {}
L 4 -0 10 8.75 18.75 {}
L 4 0 -10 20 -30 {}
B 5 17.5 -32.5 22.5 -27.5 {name=c dir=inout}
B 5 -22.5 -2.5 -17.5 2.5 {name=b dir=in}
B 5 17.5 27.5 22.5 32.5 {name=e dir=inout}
P 4 4 17.5 27.5 13.75 13.75 3.75 23.75 17.5 27.5 {fill=true}
T {area=@area} 20 -20 0 0 0.2 0.2 {}
T {@symname} 20 -5 0 0 0.2 0.2 {}
T {@name} 20 10 0 0 0.2 0.2 {}
