# verilator Arguments

The following arguments may be passed to the “verilator” executable.

Summary:

>     <file.v>                    Verilog package, module, and top module filenames
>     <file.c/cc/cpp>             Optional C++ files to compile in
>     <file.a/o/so>               Optional C++ files to link in

>      +1364-1995ext+<ext>        Use Verilog 1995 with file extension <ext>
>      +1364-2001ext+<ext>        Use Verilog 2001 with file extension <ext>
>      +1364-2005ext+<ext>        Use Verilog 2005 with file extension <ext>
>      +1800-2005ext+<ext>        Use SystemVerilog 2005 with file extension <ext>
>      +1800-2009ext+<ext>        Use SystemVerilog 2009 with file extension <ext>
>      +1800-2012ext+<ext>        Use SystemVerilog 2012 with file extension <ext>
>      +1800-2017ext+<ext>        Use SystemVerilog 2017 with file extension <ext>
>     --assert                    Enable all assertions
>     --autoflush                 Flush streams after all $displays
>     --bbox-sys                  Blackbox unknown $system calls
>     --bbox-unsup                Blackbox unsupported language features
>     --binary                    Build model binary
>     --build                     Build model executable/library after Verilation
>     --build-dep-bin <filename>  Override build dependency Verilator binary
>     --build-jobs <jobs>         Parallelism for --build
>     --cc                        Create C++ output
>     --cdc                       Clock domain crossing analysis
>      -CFLAGS <flags>            C++ compiler arguments for makefile
>     --clk <signal-name>         Mark specified signal as clock
>     --no-clk <signal-name>      Prevent marking specified signal as clock
>     --compiler <compiler-name>  Tune for specified C++ compiler
>     --converge-limit <loops>    Tune convergence settle time
>     --coverage                  Enable all coverage
>     --coverage-line             Enable line coverage
>     --coverage-max-width <width>   Maximum array depth for coverage
>     --coverage-toggle           Enable toggle coverage
>     --coverage-underscore       Enable coverage of _signals
>     --coverage-user             Enable SVL user coverage
>      -D<var>[=<value>]          Set preprocessor define
>     --debug                     Enable debugging
>     --debug-check               Enable debugging assertions
>     --no-debug-leak             Disable leaking memory in --debug mode
>     --debugi <level>            Enable debugging at a specified level
>     --debugi-<srcfile> <level>  Enable debugging a source file at a level
>     --no-decoration             Disable comments and symbol decorations
>     --default-language <lang>   Default language to parse
>      +define+<var>=<value>      Set preprocessor define
>     --dpi-hdr-only              Only produce the DPI header file
>     --dump-defines              Show preprocessor defines with -E
>     --dump-dfg                  Enable dumping DfgGraphs to .dot files
>     --dump-graph                Enable dumping V3Graphs to .dot files
>     --dump-tree                 Enable dumping Ast .tree files
>     --dump-tree-addrids         Use short identifiers instead of addresses
>     --dump-<srcfile>            Enable dumping everything in source file
>     --dumpi-dfg <level>         Enable dumping DfgGraphs to .dot files at level
>     --dumpi-graph <level>       Enable dumping V3Graphs to .dot files at level
>     --dumpi-tree <level>        Enable dumping Ast .tree files at level
>     --dumpi-<srcfile> <level>   Enable dumping everything in source file at level
>      -E                         Preprocess, but do not compile
>     --error-limit <value>       Abort after this number of errors
>     --exe                       Link to create executable
>     --expand-limit <value>      Set expand optimization limit
>      -F <file>                  Parse arguments from a file, relatively
>      -f <file>                  Parse arguments from a file
>      -FI <file>                 Force include of a file
>     --flatten                   Force inlining of all modules, tasks and functions
>      -fno-<optimization>        Disable internal optimization stage
>      -G<name>=<value>           Overwrite top-level parameter
>     --gate-stmts <value>        Tune gate optimizer depth
>     --gdb                       Run Verilator under GDB interactively
>     --gdbbt                     Run Verilator under GDB for backtrace
>     --generate-key              Create random key for --protect-key
>     --getenv <var>              Get environment variable with defaults
>     --get-supported <feature>   Get if feature is supported
>     --help                      Display this help
>     --hierarchical              Enable hierarchical Verilation
>      -I<dir>                    Directory to search for includes
>     --if-depth <value>          Tune IFDEPTH warning
>      +incdir+<dir>              Directory to search for includes
>     --inline-mult <value>       Tune module inlining
>     --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
>      -j <jobs>                  Parallelism for --build-jobs/--verilate-jobs
>     --l2-name <value>           Verilog scope name of the top module
>     --language <lang>           Default language standard to parse
>      -LDFLAGS <flags>           Linker pre-object arguments for makefile
>     --lib-create <name>         Create a DPI library
>      +libext+<ext>+[ext]...     Extensions for finding modules
>     --lint-only                 Lint, but do not make output
>     --make <build-tool>         Generate scripts for specified build tool
>      -MAKEFLAGS <flags>         Arguments to pass to make during --build
>     --main                      Generate C++ main() file
>     --main-top-name             Specify top name passed to Verilated model in generated C++ main
>     --max-num-width <value>     Maximum number width (default: 64K)
>     --Mdir <directory>          Name of output object directory
>     --MMD                       Create .d dependency files
>     --mod-prefix <topname>      Name to prepend to lower classes
>     --MP                        Create phony dependency targets
>      +notimingchecks            Ignored
>      -O0                        Disable optimizations
>      -O3                        High-performance optimizations
>      -O<optimization-letter>    Selectable optimizations
>      -o <executable>            Name of final executable
>     --no-order-clock-delay      Disable ordering clock enable assignments
>     --output-split <statements>          Split .cpp files into pieces
>     --output-split-cfuncs <statements>   Split model functions
>     --output-split-ctrace <statements>   Split tracing functions
>      -P                         Disable line numbers and blanks with -E
>     --pins-bv <bits>            Specify types for top-level ports
>     --pins-sc-biguint           Specify types for top-level ports
>     --pins-sc-uint              Specify types for top-level ports
>     --pins-uint8                Specify types for top-level ports
>     --no-pins64                 Don't use uint64_t's for 33-64 bit sigs
>     --pipe-filter <command>     Filter all input through a script
>     --pp-comments               Show preprocessor comments with -E
>     --prefix <topname>          Name of top-level class
>     --private                   Debugging; see docs
>     --prof-c                    Compile C++ code with profiling
>     --prof-cfuncs               Name functions for profiling
>     --prof-exec                 Enable generating execution profile for gantt chart
>     --prof-pgo                  Enable generating profiling data for PGO
>     --protect-ids               Hash identifier names for obscurity
>     --protect-key <key>         Key for symbol protection
>     --protect-lib <name>        Create a DPI protected library
>     --public                    Debugging; see docs
>     --public-params             Mark all parameters as public_flat
>     --public-flat-rw            Mark all variables, etc as public_flat_rw
>      -pvalue+<name>=<value>     Overwrite toplevel parameter
>     --quiet-exit                Don't print the command on failure
>     --relative-includes         Resolve includes relative to current file
>     --reloop-limit              Minimum iterations for forming loops
>     --report-unoptflat          Extra diagnostics for UNOPTFLAT
>     --rr                        Run Verilator and record with rr
>     --savable                   Enable model save-restore
>     --sc                        Create SystemC output
>     --no-skip-identical         Disable skipping identical output
>     --stats                     Create statistics file
>     --stats-vars                Provide statistics on variables
>     --no-std                    Prevent parsing standard library
>     --structs-packed            Convert all unpacked structures to packed structures
>      -sv                        Enable SystemVerilog parsing
>      +systemverilogext+<ext>    Synonym for +1800-2017ext+<ext>
>     --threads <threads>         Enable multithreading
>     --threads-dpi <mode>        Enable multithreaded DPI
>     --threads-max-mtasks <mtasks>  Tune maximum mtask partitioning
>     --timing                    Enable timing support
>     --no-timing                 Disable timing support
>     --timescale <timescale>     Sets default timescale
>     --timescale-override <timescale>  Overrides all timescales
>     --top <topname>             Alias of --top-module
>     --top-module <topname>      Name of top-level input module
>     --trace                     Enable waveform creation
>     --trace-coverage            Enable tracing of coverage
>     --trace-depth <levels>      Depth of tracing
>     --trace-fst                 Enable FST waveform creation
>     --trace-max-array <depth>   Maximum bit width for tracing
>     --trace-max-width <width>   Maximum array depth for tracing
>     --trace-params              Enable tracing of parameters
>     --trace-structs             Enable tracing structure names
>     --trace-threads <threads>   Enable FST waveform creation on separate threads
>     --no-trace-top              Do not emit traces for signals in the top module generated by verilator
>     --trace-underscore          Enable tracing of _signals
>      -U<var>                    Undefine preprocessor define
>     --no-unlimited-stack        Don't disable stack size limit
>     --unroll-count <loops>      Tune maximum loop iterations
>     --unroll-stmts <stmts>      Tune maximum loop body size
>     --unused-regexp <regexp>    Tune UNUSED lint signals
>      -V                         Verbose version and config
>      -v <filename>              Verilog library
>     --verilate-jobs             Job threads for Verilation stage
>     --no-verilate               Skip Verilation and just compile previously Verilated code
>      +verilog1995ext+<ext>      Synonym for +1364-1995ext+<ext>
>      +verilog2001ext+<ext>      Synonym for +1364-2001ext+<ext>
>     --version                   Displays program version and exits
>     --vpi                       Enable VPI compiles
>     --waiver-output <filename>  Create a waiver file based on the linter warnings
>      -Wall                      Enable all style warnings
>      -Werror-<message>          Convert warnings to errors
>      -Wfuture-<message>         Disable unknown message warnings
>      -Wno-<message>             Disable warning
>      -Wno-context               Disable source context on warnings
>      -Wno-fatal                 Disable fatal exit on warnings
>      -Wno-lint                  Disable all lint warnings
>      -Wno-style                 Disable all style warnings
>      -Wpedantic                 Warn on compliance-test issues
>      -Wwarn-<message>           Enable specified warning message
>      -Wwarn-lint                Enable lint warning message
>      -Wwarn-style               Enable style warning message
>     --x-assign <mode>           Assign non-initial Xs to this value
>     --x-initial <mode>          Assign initial Xs to this value
>     --x-initial-edge            Enable initial X->0 and X->1 edge triggers
>     --xml-only                  Create XML parser output
>     --xml-output                XML output filename
>      -y <dir>                   Directory to search for modules

<file.v>

  Specifies the Verilog file containing the top module to be Verilated.

<file.c/.cc/.cpp/.cxx>

  Used with `--exe` to specify optional C++ files to be linked in with the Verilog code. The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile’s VPATH the appropriate directory to find the file.

  See also `-CFLAGS` and `-LDFLAGS` options, which are useful when the C++ files need special compiler flags.

<file.a/.o/.so>

  Specifies optional object or library files to be linked with the Verilog code, as a shorthand for `-LDFLAGS <file>`. The file path should either be absolute, or relative to where the make will be executed from, or add the appropriate directory to your makefile’s VPATH to find the file.

  If any files are specified in this way, Verilator will include a make rule that uses these files when linking the module’s executable. This generally is only useful when used with the `--exe` option.

+1364-1995ext+<ext>

+1364-2001ext+<ext>

+1364-2005ext+<ext>

+1800-2005ext+<ext>

+1800-2009ext+<ext>

+1800-2012ext+<ext>

+1800-2017ext+<ext>

  Specifies the language standard to be used with a specific filename extension, <ext>.

  For compatibility with other simulators, see also the synonyms `+verilog1995ext+<ext>`, `+verilog2001ext+<ext>`, and `+systemverilogext+<ext>`.

  For any source file, the language specified by these options takes precedence over any language specified by the `--default-language` or `--language` options.

  These options take effect in the order they are encountered. Thus the following would use Verilog 1995 for `a.v` and Verilog 2001 for `b.v`:

      verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v

  These options are only recommended for legacy mixed language designs, as the preferable option is to edit the code to repair new keywords, or add appropriate ``begin_keywords`.

  Note

  ``begin_keywords` is a SystemVerilog construct, which specifies only the set of keywords to be recognized. This also controls some error messages that vary between language standards. At present, Verilator tends to be overly permissive, e.g., it will accept many grammar and other semantic extensions which might not be legal when set to an older standard.

--assert

  Enable all assertions.

--autoflush

  After every $display or $fdisplay, flush the output stream. This ensures that messages will appear immediately but may reduce performance. For best performance, call `fflush(stdout)` occasionally in the C++ main loop. Defaults to off, which will buffer output as provided by the normal C/C++ standard library IO.

--bbox-sys

  Black box any unknown $system task or function calls. System tasks will become no-operations, and system functions will be replaced with unsized zero. Arguments to such functions will be parsed, but not otherwise checked. This prevents errors when linting in the presence of company-specific PLI calls.

  Using this argument will likely cause incorrect simulation.

--bbox-unsup

  Black box some unsupported language features, currently UDP tables, the cmos and tran gate primitives, deassign statements, and mixed edge errors. This may enable linting of the rest of the design even when unsupported constructs are present.

  Using this argument will likely cause incorrect simulation.

--binary

  Create a Verilated simulator binary. Alias for `--main` `--exe` `--build` `--timing`.

  See also `-j`.

--build

  After generating the SystemC/C++ code, Verilator will invoke the toolchain to build the model library (and executable when `--exe` is also used). Verilator manages the build itself, and for this –build requires GNU Make to be available on the platform.

  `--build` cannot be specified when using `-E`, `--dpi-hdr-only`, `--lint-only`, or `--xml-only`.

--build-dep-bin <filename>

  Rarely needed. When a dependency (.d) file is created, this filename will become a source dependency, such that a change in this binary will have `make` rebuild the output files. Defaults to the full path to the Verilator binary.

  This option was named –bin before version 4.228.

--build-jobs [<value>]

  Specify the level of parallelism for `--build`. If zero, uses the number of threads in the current hardware. Otherwise, the <value> must be a positive integer specifying the maximum number of parallel build jobs.

  This forms the make option `-j` value, unless the `MAKEFLAGS` environment variable contains `-jobserver-auth`, in which case Verilator assumes that make’s jobserver is being used.

  See also `-j`.

--cc

  Specify C++ without SystemC output mode; see also the `--sc` option.

-CFLAGS <flags>

  Add specified C compiler argument to the generated makefiles. For multiple flags, either pass them as a single argument with space separators quoted in the shell (-CFLAGS "-a -b"), or use multiple -CFLAGS options (-CFLAGS -a -CFLAGS -b).

  When make is run on the generated makefile, these will be passed to the C++ compiler (g++/clang++/msvc++).

--clk <signal-name>

  With `--clk`, the specified signal is marked as a clock signal.

  The provided signal name is specified using a RTL hierarchy path. For example, v.foo.bar. If the signal is the input to top-module, then directly provide the signal name. Alternatively, use a `/*verilator clocker*/` metacomment in RTL file to mark the signal directly.

  If clock signals are assigned to vectors and later used as individual bits, Verilator will attempt to decompose the vector and connect the single-bit clock signals.

  In versions before 5.000, the clocker attribute is useful in cases where Verilator does not properly distinguish clock signals from other data signals. Using clocker will cause the signal indicated to be considered a clock, and remove it from the combinatorial logic reevaluation checking code. This may greatly improve performance.

--no-clk <signal-name>

  Prevent the specified signal from being marked as a clock. See `--clk`.

--compiler <compiler-name>

  Enables workarounds for the specified C++ compiler (list below). This does not change any performance tuning options, but it may in the future.

  clang

    Tune for clang. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in clang. This includes breaking deep structures as for msvc, as described below.

  gcc

    Tune for GNU C++, although generated code should work on almost any compliant C++ compiler. Currently, the default.

  msvc

    Tune for Microsoft Visual C++. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in MSVC++. This includes breaking deeply nested parenthesized expressions into sub-expressions to avoid error C1009, and breaking deep blocks into functions to avoid error C1061.

--converge-limit <loops>

  Rarely needed. Specifies the maximum number of runtime iterations before creating a model failed to converge error. Defaults to 100.

--coverage

  Enables all forms of coverage, an alias for `--coverage-line` `--coverage-toggle` `--coverage-user`.

--coverage-line

  Enables basic block line coverage analysis. See Line Coverage.

--coverage-max-width <width>

  Rarely needed. Specify the maximum bit width of a signal subject to toggle coverage. Defaults to 256, as covering large vectors may greatly slow coverage simulations.

--coverage-toggle

  Enables adding signal toggle coverage. See Toggle Coverage.

--coverage-underscore

  Enable coverage of signals that start with an underscore. Normally, these signals are not covered. See also `--trace-underscore` option.

--coverage-user

  Enables adding user-inserted functional coverage. See Functional Coverage.

-D<var>=<value>

  Defines the given preprocessor symbol. Similar to `+define`, but does not allow multiple definitions with a single option using plus signs. “+define” is relatively standard across Verilog tools, while “-D” is similar to gcc -D.

--debug

  Run under debug.

  - Select the debug executable of Verilator (if available). This generally is a less-optimized binary with symbols present (so GDB can be used on it).

  - Enable debugging messages (equivalent to `--debugi 3`).

  - Enable internal assertions (equivalent to `--debug-check`).

  - Enable intermediate form dump files (equivalent to `--dumpi-tree 3`).

  - Leak to make node numbers unique (equivalent to `--debug-leak`.

  - Call abort() instead of exit() if there are any errors (so GDB can see the program state).

--debug-check

  Rarely needed. Enable internal debugging assertion checks, without changing debug verbosity. Enabled automatically with `--debug` option.

--no-debug-leak

  In `--debug` mode, by default, Verilator intentionally leaks AstNode instances instead of freeing them, so that each node pointer is unique in the resulting tree files and dot files.

  This option disables the leak. This may avoid out-of-memory errors when Verilating large models in `--debug` mode.

  Outside of `--debug` mode, AstNode instances should never be leaked, and this option has no effect.

--debugi <level>

  Rarely needed - for developer use. Set the internal debugging level globally to the specified debug level (1-10). Higher levels produce more detailed messages.

--debugi-<srcfile> <level>

  Rarely needed - for developer use. Set the specified Verilator source file to the specified level (e.g., `--debugi-V3Width 9`). Higher levels produce more detailed messages. See `--debug` for other implications of enabling debug.

--no-decoration

  When creating output Verilated code, minimize comments, white space, symbol names, and other decorative items, at the cost of reduced readability. This may assist C++ compile times. This will not typically change the ultimate model’s performance, but may in some cases.

--default-language <value>

  Select the language used by default when first processing each Verilog file. The language value must be “VAMS”, “1364-1995”, “1364-2001”, “1364-2001-noconfig”, “1364-2005”, “1800-2005”, “1800-2009”, “1800-2012”, “1800-2017”, or “1800+VAMS”.

  Any language associated with a particular file extension (see the various +<lang>*ext+ options) will be used in preference to the language specified by `--default-language`.

  The `--default-language` is only recommended for legacy code using the same language in all source files, as the preferable option is to edit the code to repair new keywords, or add appropriate ``begin_keywords`. For legacy mixed-language designs, the various `+<lang>ext+` options should be used.

  If no language is specified, either by this option or `+<lang>ext+` options, then the latest SystemVerilog language (IEEE 1800-2017) is used.

+define+<var>=<value>

+define+<var>=<value>[+<var2>=<value2>][...]

  Defines the given preprocessor symbol, or multiple symbols if separated by plus signs. Similar to `-D`; +define is relatively standard across Verilog tools while `-D` is similar to gcc -D.

--dpi-hdr-only

  Only generate the DPI header file. This option does not affect on the name or location of the emitted DPI header file, it is output in `--Mdir` as it would be without this option.

--dump-defines

  With `-E`, suppress normal output, and instead print a list of all defines existing at the end of pre-processing the input files. Similar to GCC “-dM” option. This also gives you a way of finding out what is predefined in Verilator using the command:

      touch foo.v ; verilator -E --dump-defines foo.v

--dump-dfg

  Rarely needed. Enable dumping DfgGraph .dot debug files with dumping level 3.

--dump-graph

  Rarely needed. Enable dumping V3Graph .dot debug files with dumping level 3. Before Verilator 4.228, `--dump-tree` used to include this option.

--dump-tree

  Rarely needed. Enable dumping Ast .tree debug files with dumping level 3, which dumps the standard critical stages. For details on the format, see the Verilator Internals manual. `--dump-tree` is enabled automatically with `--debug`, so `--debug --no-dump-tree` may be useful if the dump files are large and not desired.

--dump-tree-dot

  Rarely needed. Enable dumping Ast .tree.dot debug files in Graphviz Dot format. This option implies `--dump-tree`, unless `--dumpi-tree` was passed explicitly.

--dump-tree-addrids

  Rarely needed - for developer use. Replace AST node addresses with short identifiers in tree dumps to enhance readability. Each unique pointer value is mapped to a unique identifier, but note that this is not necessarily unique per node instance as an address might get reused by a newly allocated node after a node with the same address has been dumped and then freed.

--dump-<srcfile>

  Rarely needed - for developer use. Enable all dumping in the given source file at level 3.

--dumpi-dfg <level>

  Rarely needed - for developer use. Set the internal DfgGraph dumping level globally to the specified value.

--dumpi-graph <level>

  Rarely needed - for developer use. Set internal V3Graph dumping level globally to the specified value.

--dumpi-tree <level>

  Rarely needed - for developer use. Set internal Ast dumping level globally to the specified value.

--dumpi-<srcfile> <level>

  Rarely needed - for developer use. Set the dumping level in the specified Verilator source file to the specified value (e.g., –dumpi-V3Order 9). Level 0 disables dumps and is equivalent to –no-dump-<srcfile>. Level 9 enables the dumping of everything.

-E

  Preprocess the source code, but do not compile, similar to C++ preprocessing using gcc -E. Output is written to standard out. Beware of enabling debugging messages, as they will also go to standard out. See `--no-std`, which is implied by this.

  See also `--dump-defines`, `-P`, and `--pp-comments` options.

--error-limit <value>

  After this number of errors are encountered during Verilator run, exit. Warnings are not counted in this limit. Defaults to 50.

  It does not affect simulation runtime errors, for those, see `+verilator+error+limit+<value>`.

--exe

  Generate an executable. You will also need to pass additional .cpp files on the command line that implement the main loop for your simulation.

--expand-limit <value>

  Rarely needed. Fine-tune optimizations to set the maximum size of an expression in 32-bit words to expand into separate word-based statements.

-F <file>

  Read the specified file, and act as if all text inside it was specified as command line arguments. Any relative paths are relative to the directory containing the specified file. See also `-f` option. Note `-F` is relatively standard across Verilog tools.

-f <file>

  Read the specified file, and act as if all text inside it was specified as command line arguments. Any relative paths are relative to the current directory. See also `-F` option. Note `-f` is relatively standard across Verilog tools.

  The file may contain `//` comments which are ignored until the end of the line. It may also contain `/* .. */` comments which are ignored, be cautious that wildcards are not handled in -f files, and that `directory/*` is the beginning of a comment, not a wildcard. Any `$VAR`, `$(VAR)`, or `${VAR}` will be replaced with the specified environment variable.

-FI <file>

  Force include of the specified C++ header file. All generated C++ files will insert a #include of the specified file before any other includes. The specified file might be used to contain define prototypes of custom `VL_VPRINTF` functions, and may need to include `verilatedos.h` as this file is included before any other standard includes.

--flatten

  Force flattening of the design’s hierarchy, with all modules, tasks, and functions inlined. Typically used with `--xml-only`. Flattening large designs may require significant CPU time, memory and storage.

-fno-acyc-simp

-fno-assemble

-fno-case

-fno-combine

-fno-const

-fno-const-bit-op-tree

-fno-dedup

-fno-dfg

  Disable all use of the DFG-based combinational logic optimizer. Alias for `-fno-dfg-pre-inline` and `-fno-dfg-post-inline`.

-fno-dfg-peephole

  Disable the DFG peephole optimizer.

-fno-dfg-peephole-<pattern>

  Disable individual DFG peephole optimizer pattern.

-fno-dfg-pre-inline

  Do not apply the DFG optimizer before inlining.

-fno-dfg-post-inline

  Do not apply the DFG optimizer after inlining.

-fno-expand

-fno-gate

-fno-inline

-fno-life

-fno-life-post

-fno-localize

-fno-merge-cond

-fno-merge-cond-motion

-fno-merge-const-pool

-fno-reloop

-fno-reorder

-fno-split

-fno-subst

-fno-subst-const

-fno-table

  Rarely needed. Disables one of the internal optimization steps. These are typically used only when recommended by a maintainer to help debug or work around an issue.

-future0 <option>

  Rarely needed. Suppress an unknown Verilator option for an option that takes no additional arguments. This allows scripts written with pragmas for a later version of Verilator to run under an older version. e.g. `-future0 option --option` would on older versions that do not understand `--option` or `+option` suppress what would otherwise be an invalid option error, and on newer versions that implement `--option`, `-future0 option --option` would have the `-future0 option` ignored and the `--option` would function appropriately.

-future1 <option>

  Rarely needed. Suppress an unknown Verilator option for an option that takes an additional argument. This allows scripts written with pragmas for a later version of Verilator to run under an older version. e.g. `-future1 option --option arg` would on older versions that do not understand `--option arg` or `+option arg` suppress what would otherwise be an invalid option error, and on newer versions that implement `--option arg`, `-future1 option --option arg` would have the `-future1 option` ignored and the `--option arg` would function appropriately.

-G<name>=<value>

  Overwrites the given parameter of the top-level module. The value is limited to basic data literals:

  Verilog integer literals

    The standard Verilog integer literals are supported, so values like 32’h8, 2’b00, 4, etc., are allowed. Care must be taken that the single quote (I’) is appropriately escaped in an interactive shell, e.g., as `-GWIDTH=8'hx`.

  C integer literals

    It is also possible to use C integer notation, including hexadecimal (0x..), octal (0..), or binary (0b..) notation.

  Double literals
    Double literals must be one of the following styles:

      - contains a dot (.) (e.g., `1.23`)

      - contains an exponent (e/E) (e.g. `12e3`)

      - contains p/P for hexadecimal floating point in C99 (e.g. `0x123.ABCp1`)

  Strings

    Strings must be in double quotes (“”). They must be escaped properly on the command line, e.g., as `-GSTR=""My String""` or `-GSTR='"My String"'`.

--gate-stmts <value>

  Rarely needed. Set the maximum number of statements present in an equation for the gate substitution optimization to inline that equation.

--gdb

  Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment variable value) session. See also `--gdbbt` option.

--gdbbt

  If `--debug` is specified, run Verilator underneath a GDB process, print a backtrace on exit, and then exit GDB immediately. Without `--debug` or if GDB doesn’t seem to work, this flag is ignored. Intended for easy creation of backtraces by users; otherwise see the `--gdb` option.

--generate-key

  Generate a true-random key suitable for use with `--protect-key`, print it, and exit immediately.

--getenv <variable>

  If the variable is declared in the environment, print it and exit immediately. Otherwise, if it’s built into Verilator (e.g., VERILATOR_ROOT), print that and exit immediately. Otherwise, print a newline and exit immediately. This can be useful in makefiles. See also `-V`, and the various `*.mk` files.

--get-supported <feature>

  If the given feature is supported, print “1” and exit immediately; otherwise, print a newline and exit immediately. This can be useful in makefiles. See also `-V`, and the various `*.mk` files.

  Feature may be one of the following: COROUTINES, SYSTEMC.

--help

  Displays this message and program version and exits.

--hierarchical

  Enable hierarchical Verilation; otherwise, the `/*verilator hier_block*/` metacomment is ignored. See Hierarchical Verilation.

-I<dir>

  See `-y`.

--if-depth <value>

  Rarely needed. Set the depth at which the IFDEPTH warning will fire, defaults to 0, which disables this warning.

+incdir+<dir>

  See `-y`.

--inline-mult <value>

  Tune the inlining of modules. The default value of 2000 specifies that up to 2000 new operations may be added to the model by inlining. If more than this number of operations would result, the module is not inlined. Larger values, or a value < 1 which will inline everything, leads to longer compile times, but potentially faster simulation speed. This setting is ignored for very small modules; they will always be inlined, if allowed.

--instr-count-dpi <value>

  Tune the assumed dynamic instruction count of the average DPI import. This is used by the partitioning algorithm when creating a multithread model. The default value is 200. Adjusting this to an appropriate value can yield performance improvements in multithreaded models. Ignored when creating a single-threaded model.

-j [<value>]

  Specify the level of parallelism for `--build` if `--build-jobs` isn’t provided, and the internal compilation steps of Verilator if `--verilate-jobs` isn’t provided. If zero, uses the number of threads in the current hardware. Otherwise, must be a positive integer specifying the maximum number of parallel build jobs.

--l2-name <value>

  Instead of using the module name when showing Verilog scope, use the name provided. This allows simplifying some Verilator-embedded modeling methodologies. The default is an l2-name matching the top module, and the default before Verilator 3.884 was `--l2-name v`.

  For example, the program `module t; initial $display("%m"); endmodule` will show by default “t”. With `--l2-name v` it will print “v”.

--language <value>

  A synonym for `--default-language`, for compatibility with other tools and earlier versions of Verilator.

-LDFLAGS <flags>

  Add specified C linker arguments to the generated makefiles. For multiple flags, either pass them as a single argument with space separators quoted in the shell (`-LDFLAGS "-a -b"`), or use multiple -LDFLAGS arguments (`-LDFLAGS -a -LDFLAGS -b`).

  When make is run on the generated makefile, these will be passed to the C++ linker (ld) after the primary file being linked. This flag is called `-LDFLAGS` as that’s the traditional name in simulators; it’s would have been better called LDLIBS as that’s the Makefile variable it controls. (In Make, LDFLAGS is before the first object, LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not LDFLAGS.)

--lib-create <name>

  Produces C++, Verilog wrappers, and a Makefile which can produce a DPI library that can be used by Verilator or other simulators along with the corresponding Verilog wrapper. The Makefile will build both a static and dynamic version of the library named `lib<name>.a` and `lib<name>.so` respectively. This is done because some simulators require a dynamic library, but the static library is arguably easier to use if possible. `--protect-lib` implies `--protect-ids`.

  When using `--lib-create`, it is advised to also use `--timescale-override /1fs` to ensure the model has a time resolution that is always compatible with the time precision of the upper instantiating module.

  Designs compiled using this option cannot use `--timing` with delays.

  See also `--protect-lib`.

+libext+<ext>[+<ext>][...]

  Specify the extensions that should be used for finding modules. If for example, module “my” is referenced, look in `my.<ext>`. Note “+libext+” is relatively standard across Verilog tools. Defaults to “.v+.sv”.

--lint-only

  Check the files for lint violations only, do not create any other output.

  You may also want the `-Wall` option to enable messages considered stylistic and not enabled by default.

  If the design is not to be completely Verilated, see also the `--bbox-sys` and `--bbox-unsup` options.

--make <build-tool>

  Generates a script for the specified build tool.

  Supported values are `gmake` for GNU Make and `cmake` for CMake. Both can be specified together. If no build tool is specified, gmake is assumed. The executable of gmake can be configured via the environment variable `MAKE`.

  When using `--build`, Verilator takes over the responsibility of building the model library/executable. For this reason `--make` cannot be specified when using `--build`.

-MAKEFLAGS <string>

  When using `--build`, add the specified argument to the invoked make command line. For multiple flags, either pass them as a single argument with space separators quoted in the shell (e.g. `-MAKEFLAGS "-a -b"`), or use multiple -MAKEFLAGS arguments (e.g. `-MAKEFLAGS -l -MAKEFLAGS -k`). Use of this option should not be required for simple builds using the host toolchain.

--main

  Generates a top-level C++ main() file that supports parsing arguments, but does not drive any inputs. This is sufficient to use for top-level SystemVerilog designs that have no inputs.

  This option can also be used once to generate the main .cpp file as a starting point for editing. Copy it outside the obj directory, manually edit, and then pass the filename on later Verilator command line invocations.

  Typically used with `--timing` to support delay-generated clocks, and `--build`.

  Implies `--cc` if no other output mode was provided.

  See also `--binary`.

--main-top-name <string>

  Specify the name passed to the Verilated model being constructed, in the generated C++ main() function.

  If the string `"-"` is used, no top level scope is added.

--max-num-width <value>

  Set the maximum number literal width (e.g., in 1024’d22 this 1024). Defaults to 64K.

--Mdir <directory>

  Specifies the name of the Make object directory. All generated files will be placed in this directory. If not specified, “obj_dir” is used. The directory is created if it does not exist and the parent directories exist; otherwise, manually create the Mdir before calling Verilator.

--MMD

--no-MMD

  Enable/disable the creation of .d dependency files, used for make dependency detection, similar to gcc -MMD option. By default this option is enabled for `--cc` or `--sc` modes.

--mod-prefix <topname>

  Specifies the name to prepend to all lower-level classes. Defaults to the same as `--prefix`.

--MP

  When creating .d dependency files with `--MMD` option, make phony targets. Similar to gcc -MP option.

+notimingchecks

  Ignored for compatibility with other simulators.

-O0

  Disables optimization of the model.

-O3

  Enables slow optimizations for the code Verilator itself generates (as opposed to `-CFLAGS -O3` which affects the C compiler’s optimization. `-O3` may improve simulation performance at the cost of compile time. This currently sets `--inline-mult -1`.

-O<optimization-letter>

  Rarely needed. Enables or disables specific optimizations, with the optimization selected based on the letter passed. A lowercase letter disables an optimization, an uppercase letter enables it. This option is deprecated and the various -f<optimization> arguments should be used instead.

-o <executable>

  Specify the name for the final executable built if using `--exe`. Defaults to the `--prefix` if not specified.

--no-order-clock-delay

  Deprecated and has no effect (ignored).

  In versions before 5.000:

  Rarely needed. Disables a bug fix for ordering of clock enables with delayed assignments. This option should only be used when suggested by the developers.

--output-split <statements>

  Enables splitting the output .cpp files into multiple outputs. When a C++ file exceeds the specified number of operations, a new file will be created at the next function boundary. In addition, if the total output code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to 1 by default in the generated makefiles, making parallel compilation possible. Using `--output-split` should have only a trivial impact on model performance. But can greatly improve C++ compilation speed. The use of “ccache” (set for you if present at configure time) is also more effective with this option.

  This option is on by default with a value of 20000. To disable, pass with a value of 0.

--output-split-cfuncs <statements>

  Enables splitting functions in the output .cpp files into multiple functions. When a generated function exceeds the specified number of operations, a new function will be created. With `--output-split`, this will enable the C++ compiler to compile faster, at a small loss in performance that gets worse with decreasing split values. Note that this option is stronger than `--output-split` in the sense that `--output-split` will not split inside a function.

  Defaults to the value of `--output-split`, unless explicitly specified.

--output-split-ctrace <statements>

  Similar to `--output-split-cfuncs`, it enables splitting trace functions in the output .cpp files into multiple functions.

  Defaults to the value of `--output-split`, unless explicitly specified.

-P

  With `-E`, disable generation of ``line` markers and blank lines, similar to gcc -P.

--pins-bv <width>

  Specifies SystemC inputs/outputs greater than or equal to <width> bits wide should use sc_bv’s instead of uint32/uint64_t’s. The default is “–pins-bv 65”, and the value must be less than or equal to 65. Versions before Verilator 3.671 defaulted to “–pins-bv 33”. The more sc_bv is used, the worse for performance. Use the `/*verilator sc_bv*/` metacomment to select specific ports to be sc_bv.

--pins-sc-uint

  Specifies SystemC inputs/outputs greater than 2 bits wide should use sc_uint between 2 and 64. When combined with the `--pins-sc-biguint` combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512.

--pins-sc-biguint

  Specifies SystemC inputs/outputs greater than 65 bits wide should use sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined with the `--pins-sc-uint` combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512.

--pins-uint8

  Specifies SystemC inputs/outputs smaller than the `--pins-bv` setting and 8 bits or less should use uint8_t instead of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of uint32_t.

--pins64

  Backward compatible alias for `--pins-bv 65`. Note that’s a 65, not a 64.

--no-pins64

  Backward compatible alias for `--pins-bv 33`.

--pipe-filter <command>

  Rarely needed. Verilator will spawn the specified command as a subprocess pipe, to allow the command to perform custom edits on the Verilog code before it reaches Verilator.

  Before reading each Verilog file, Verilator will pass the file name to the subprocess’ stdin with `read "<filename>"`. The filter may then read the file and perform any filtering it desires, and feeds the new file contents back to Verilator on stdout by first emitting a line defining the length in bytes of the filtered output `Content-Length: <bytes>`, followed by the new filtered contents. Output to stderr from the filter feeds through to Verilator’s stdout and if the filter exits with non-zero status Verilator terminates. See the file:t/t_pipe_filter test for an example.

  To debug the output of the filter, try using the `-E` option to see the preprocessed output.

--pp-comments

  With `-E`, show comments in preprocessor output.

--prefix <topname>

  Specifies the name of the top-level class and makefile. Defaults to V prepended to the name of the `--top` option, or V prepended to the first Verilog filename passed on the command line.

--private

  Opposite of `--public`. This is the default; this option exists for backwards compatibility.

--prof-c

  When compiling the C++ code, enable the compiler’s profiling flag (e.g., `g++ -pg`). See Code Profiling.

  Using `--prof-cfuncs` also enables `--prof-c`.

--prof-cfuncs

  Modify the created C++ functions to support profiling. The functions will be minimized to contain one “basic” statement, generally a single always block or wire statement. (This may slow down the executable by ~5%.) Furthermore, the function name will be suffixed with the basename of the Verilog module and the line number the statement came from. This allows gprof or oprofile reports to be correlated with the original Verilog source statements. See Code Profiling.

  Using `--prof-cfuncs` also enables `--prof-c`.

--prof-exec

  Enable collection of execution trace, that can be converted into a gantt chart with verilator_gantt See Execution Profiling.

--prof-pgo

  Enable collection of profiling data for profile-guided Verilation. Currently, this is only useful with `--threads`. See Thread Profile-Guided Optimization.

--prof-threads

  Removed in 5.020. Was an alias for –prof-exec and –prof-pgo together.

--protect-ids

  Hash any private identifiers (variable, module, and assertion block names that are not on the top-level) into hashed random-looking identifiers, resulting after compilation in protected library binaries that expose less design information. This hashing uses the provided or default `--protect-key`; see important details there.

  Verilator will also create a `<prefix>__idmap.xml` file which contains the mapping from the hashed identifiers back to the original identifiers. This idmap file is to be kept private, and is to assist in mapping any simulation runtime design assertions, coverage, or trace information, which will report the hashed identifiers, back to the original design’s identifier names.

  Using DPI imports/exports are allowed and generally relatively safe in terms of information disclosed, which is limited to the DPI function prototypes. Use of the VPI is not recommended as many design details may be exposed, and an INSECURE warning will be issued.

--protect-key <key>

  Specifies the private key for `--protect-ids`. For best security this key should be 16 or more random bytes, a reasonable secure choice is the output of verilator --generate-key . Typically, a key would be created by the user once for a given protected design library, then every Verilator run for subsequent versions of that library would be passed the same `--protect-key`. Thus, if the input Verilog is similar between library versions (Verilator runs), the Verilated code will likewise be mostly similar.

  If `--protect-key` is not specified and a key is needed, Verilator will generate a new key for every Verilator run. As the key is not saved, this is best for security, but means every Verilator run will give vastly different output even for identical input, perhaps harming compile times (and certainly thrashing any “ccache”).

--protect-lib <name>

  Produces a DPI library similar to `--lib-create`, but hides internal design details. `--protect-lib` implies `--protect-ids`, and `--lib-create`.

  This allows for the secure delivery of sensitive IP without the need for encrypted RTL (i.e. IEEE P1735). See `examples/make_protect_lib` in the distribution for a demonstration of how to build and use the DPI library.

  Designs compiled using this option cannot use `--timing` with delays.

--public

  This is only for historical debugging use and using it may result in mis-simulation of generated clocks.

  Declares all signals and modules public. This will turn off signal optimizations as if all signals had a `/*verilator public*/` metacomments and inlining. This will also turn off inlining as if all modules had a `/*verilator public_module*/`, unless the module specifically enabled it with `/*verilator inline_module*/`.

--public-flat-rw

  Declares all variables, ports, and wires public as if they had `/*verilator public_flat_rw @ (<variable's_source_process_edge>)*/` metacomments. This will make them VPI accessible by their flat name, but not turn off module inlining. This is particularly useful in combination with `--vpi`. This may also in some rare cases result in mis-simulation of generated clocks. Instead of this global option, marking only those signals that need public_flat_rw is typically significantly better performing.

--public-depth <level>

  Enables public as with `--public-flat-rw`, but only to the specified depth of modules. It operates at the module maximum level, so if a module’s cells are A.B.X and A.X, the a –public-depth 3 must be used to make module X public, and both A.B.X and A.X will be public.

--public-params

  Declares all parameters public as if they had `/*verilator public_flat_rd*/` metacomments.

-pvalue+<name>=<value>

  Overwrites the given parameter(s) of the top-level module. See `-G` for a detailed description.

--quiet-exit

  When exiting due to an error, do not display the “Exiting due to Errors” nor “Command Failed” messages.

--relative-includes

  When a file references an include file, resolve the filename relative to the path of the referencing file, instead of relative to the current directory.

--reloop-limit

  Rarely needed. Verilator attempts to turn some common sequences of statements into loops in the output. This argument specifies the minimum number of iterations the resulting loop needs to have to perform this transformation. The default limit is 40. A smaller number may slightly improve C++ compilation time on designs where these sequences are common; however, the effect on model performance requires benchmarking.

--report-unoptflat

  Enable extra diagnostics for `UNOPTFLAT` warnings. This includes, for each loop, the ten widest variables in the loop, and the ten most fanned-out variables in the loop. These are candidates for splitting into multiple variables to break the loop.

  In addition, produces a GraphViz DOT file of the entire strongly connected components within the source associated with each loop. This is produced irrespective of whether `--dump-tree` is set. Such graphs may help analyze the problem, but can be very large.

  Various commands exist for viewing and manipulating DOT files, for example, the “dot” command can convert a DOT file to a PDF for printing. For example:

      dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot

  will generate a PDF `Vt_unoptflat_simple_2_35_unoptflat.dot.pdf` from the DOT file.

  As an alternative, the xdot command can be used to view DOT files interactively:

      xdot Vt_unoptflat_simple_2_35_unoptflat.dot

--rr

  Run Verilator and record with the rr command. See https://rr-project.org.

--savable

  Enable including save and restore functions in the generated model. See Save/Restore.

--sc

  Specifies SystemC output mode; see also `--cc` option.

--skip-identical

--no-skip-identical

  Rarely needed. Disables or enables skipping execution of Verilator if all source files are identical, and all output files exist with newer dates. By default, this option is enabled for `--cc` or `--sc` modes only.

--stats

  Creates a dump file with statistics on the design in `<prefix>__stats.txt`.

--stats-vars

  Creates more detailed statistics, including a list of all the variables by size (plain `--stats` just gives a count). See `--stats`, which is implied by this.

--no-std

  Prevents parsing standard library.

--structs-packed

  Converts all unpacked structures to packed structures, and issues an `UNPACKED` warning. Specifying this option allows for backward compatibility with versions before Verilator 5.006, when Verilator would always pack unpacked structures.

-sv

  Specifies SystemVerilog language features should be enabled; equivalent to `--language 1800-2017`. This option is selected by default; it exists for compatibility with other simulators.

+systemverilogext+<ext>

  A synonym for `+1800-2017ext+<ext>`.

--threads <threads>

  With “–threads 1”, the default, the generated model is single-threaded but may run in a multithreaded environment. With “–threads N”, where N >= 2, the model is generated to run multithreaded on up to N threads. See Multithreading. This option also applies to `--trace` (but not `--trace-fst`).

--no-threads

  Deprecated and has no effect (ignored).

  In versions before 5.004, created a model which was not thread-safe.

--threads-dpi all

--threads-dpi none

--threads-dpi pure

  When using `--threads`, controls which DPI imported tasks and functions are considered thread-safe.

  With “–threads-dpi all”,

    Enable Verilator to assume all DPI imports are thread-safe, and to use thread-local storage for communication with DPI, potentially improving performance. Any DPI libraries need appropriate mutexes to avoid undefined behavior.

  With “–threads-dpi none”,

    Verilator assumes DPI imports are not thread-safe, and Verilator will serialize calls to DPI imports by default, potentially harming performance.

  With “–threads-dpi pure”, the default,

    Verilator assumes DPI pure imports are thread-safe, but non-pure DPI imports are not.

  See also `--instr-count-dpi` option.

--threads-max-mtasks <value>

  Rarely needed. When using `--threads`, specify the number of mtasks the model is to be partitioned into. If unspecified, Verilator approximates a good value.

--timescale <timeunit>/<timeprecision>

  Sets default timeunit and timeprecision when “timescale” does not occur before a given module. Default is “1ps/1ps” (to match SystemC). This is overridden by :vlopt:–timescale-override`.

--timescale-override <timeunit>/<timeprecision>

--timescale-override /<timeprecision>

  Overrides all “`timescale”s in sources. The timeunit may be left empty to specify only to override the timeprecision, e.g. “/1fs”.

  The time precision must be consistent with SystemC’s “sc_set_time_resolution()”, or the C++ code instantiating the Verilated module. As “1fs” is the finest time precision, it may be desirable always to use a precision of “1fs”.

--timing

--no-timing

  Enables/disables support for timing constructs such as delays, event controls (unless it’s at the top of a process), wait statements, and joins. When disabled, timing control constructs are ignored the same way as in earlier versions of Verilator. Enabling this feature requires a C++ compiler with coroutine support (GCC 10, Clang 5, or newer).

--top <topname>

--top-module <topname>

  When the input Verilog contains more than one top-level module, it specifies the name of the module to become the top-level module, and sets the default for `--prefix` if not explicitly specified. This is not needed with standard designs with only one top. See also `MULTITOP` warning.

--trace

  Adds waveform tracing code to the model using VCD format. This overrides `--trace-fst`.

  Verilator will generate additional `<prefix>__Trace*.cpp` files must be compiled. In addition `verilated_vcd_sc.cpp` (for SystemC traces) or `verilated_vcd_c.cpp` (for both) must be compiled and linked in. If using the Verilator-generated Makefiles, these files will be added to the source file lists for you. If you are not using the Verilator Makefiles, you will need to add these to your Makefile manually.

  Having tracing compiled in may result in small performance losses, even when tracing is not turned on during model execution.

  When using `--threads`, VCD tracing is parallelized, using the same number of threads as passed to `--threads`.

--trace-coverage

  With `--trace` and `--coverage-*`, enable tracing to include a traced signal for every `--coverage-line` or `--coverage-user`-inserted coverage point, to assist in debugging coverage items. Note `--coverage-toggle` does not get additional signals added, as the original signals being toggle-analyzed are already visible.

  The added signal will be a 32-bit value, incrementing on each coverage occurrence. Due to this, this option may significantly increase trace file sizes and reduce simulation speed.

--trace-depth <levels>

  Specify the number of levels deep to enable tracing, for example, `--trace-depth 1` to only see the top-level signals. Defaults to the entire model. Using a small number will decrease visibility, but significantly improve simulation performance and trace file size.

--trace-fst

  Enable FST waveform tracing in the model. This overrides `--trace`. See also `--trace-threads` option.

--trace-max-array <depth>

  Rarely needed. Specify the maximum array depth of a signal that may be traced. Defaults to 32, as tracing large arrays may greatly slow traced simulations.

--trace-max-width <width>

  Rarely needed. Specify the maximum bit width of a signal that may be traced. Defaults to 256, as tracing large vectors may greatly slow traced simulations.

--no-trace-params

  Disable tracing of parameters.

--trace-structs

  Enable tracing to show the name of packed structure, union, and packed array fields, rather than a single combined packed bus. Due to VCD file format constraints, this may result in significantly slower trace times and larger trace files.

--trace-threads <threads>

  Enable waveform tracing using separate threads. This is typically faster in simulation runtime but uses more total compute. This option only applies to `--trace-fst`. FST tracing can utilize at most “–trace-threads 2”. This overrides `--no-threads`.

  This option is accepted, but has absolutely no effect with `--trace`, which respects `--threads` instead.

--no-trace-top

  Disables tracing for the input and output signals in the top wrapper which Verilator adds to the design. The signals are still traced in the original verilog top modules.

  When combined with `--main-top-name` set to “-” or when the name of the top module is set to “” in its constructor, the generated trace file will have the verilog top module as its root, rather than another module added by Verilator.

--trace-underscore

  Enable tracing of signals or modules that start with an underscore. Otherwise, these signals are not output during tracing. See also `--coverage-underscore` option.

-U<var>

  Undefines the given preprocessor symbol.

--no-unlimited-stack

  Verilator tries to disable stack size limit using ulimit -s unlimited command. This option turns this behavior off.

--unroll-count <loops>

  Rarely needed. Specifies the maximum number of loop iterations that may be unrolled. See also `BLKLOOPINIT` warning.

--unroll-stmts <statements>

  Rarely needed. Specifies the maximum number of statements in a loop for that loop to be unrolled. See also `BLKLOOPINIT` warning.

--unused-regexp <regexp>

  Rarely needed. Specifies a simple regexp with * and ? that, if a signal name matches, will suppress the `UNUSED` warning. Defaults to “*unused*”. Setting it to “” disables matching.

-V

  Shows the verbose version, including configuration information compiled into Verilator. (Similar to perl -V.) See also `--getenv` option.

-v <filename>

  Read the filename as a Verilog library. Any modules in the file may be used to resolve instances in the top-level module, otherwise, they are ignored. Note “-v” is relatively standard across Verilog tools.

--no-verilate

  When using `--build`, disable the generation of C++/SystemC code, and execute only the build. This can be useful for rebuilding the Verilated code produced by a previous invocation of Verilator.

--verilate-jobs [<value>]

  Specify the level of parallelism for the internal compilation steps of Verilator. If zero, uses the number of threads in the current hardware. Otherwise, must be a positive integer specifying the maximum number of parallel build jobs.

  See also `-j`.

+verilog1995ext+<ext>

  Synonym for `+1364-1995ext+<ext>`.

+verilog2001ext+<ext>

  Synonym for `+1364-2001ext+<ext>`.

--version

  Displays program version and exits.

--vpi

  Enable the use of VPI and linking against the `verilated_vpi.cpp` files.

--waiver-output <filename>

  Generate a waiver file that contains all waiver statements to suppress the warnings emitted during this Verilator run. This, in particular, is useful as a starting point for solving linter warnings or suppressing them systematically.

  The generated file is in the Verilator Configuration format, see Configuration Files. The standard file extension is “.vlt”. These files can directly be consumed by Verilator, typically by placing the filename as part of the Verilator command line options. Waiver files need to be listed on the command line before listing the files they are waiving.

-Wall

  Enable all code-style warnings, including style warnings that are typically disabled by default. Equivalent to `-Wwarn-lint` `-Wwarn-style`. Excludes some specialty warnings.

-Werror-<message>

  Promote the specified warning message into an error message. This is generally to discourage users from violating important site-wide rules, for example, “-Werror-NOUNOPTFLAT”.

-Wfuture-<message>

  Rarely needed. Suppress unknown Verilator comments or warning messages with the given message code. This is used to allow code written with pragmas for a later version of Verilator to run under an older version; add “-Wfuture-” arguments for each message code or comment that the new version supports, which the older version does not support.

-Wno-<message>

  Disable the specified warning/error message. This will override any lint_on directives in the source, i.e., the warning will still not be printed.

-Wno-context

  Disable showing the suspected context of the warning message by quoting the source text at the suspected location. This can be used to appease tools that process the warning messages but may get confused by lines quoted from the source.

-Wno-fatal

  When warnings are detected, print them, but do not terminate Verilator.

  Having warning messages in builds can be sloppy. You should cleanup your code, use inline lint_off, or use `-Wno-...` options rather than using this option.

-Wno-lint

  Disable all lint-related warning messages, and all style warnings. This is equivalent to `-Wno-ALWCOMBORDER` `-Wno-ASCRANGE` `-Wno-BSSPACE` `-Wno-CASEINCOMPLETE` `-Wno-CASEOVERLAP` `-Wno-CASEX` `-Wno-CASTCONST` `-Wno-CASEWITHX` `-Wno-CMPCONST` `-Wno-COLONPLUS` `-Wno-IMPLICIT` `-Wno-IMPLICITSTATIC` `-Wno-PINCONNECTEMPTY` `-Wno-PINMISSING` `-Wno-STATICVAR` `-Wno-SYNCASYNCNET` `-Wno-UNDRIVEN` `-Wno-UNSIGNED` `-Wno-UNUSEDGENVAR` `-Wno-UNUSEDPARAM` `-Wno-UNUSEDSIGNAL` `-Wno-WIDTH`, plus the list shown for `-Wno-style`.

  It is strongly recommended that you clean up your code rather than using this option; it is only intended to be used when running test-cases of code received from third parties.

-Wno-style

  Disable all code style related warning messages (note that by default, they are already disabled). This is equivalent to `-Wno-DECLFILENAME` `-Wno-DEFPARAM` `-Wno-EOFNEWLINE` `-Wno-GENUNNAMED` `-Wno-IMPORTSTAR` `-Wno-INCABSPATH` `-Wno-PINCONNECTEMPTY` `-Wno-PINNOCONNECT` `-Wno-SYNCASYNCNET` `-Wno-UNDRIVEN` `-Wno-UNUSEDGENVAR` `-Wno-UNUSEDPARAM` `-Wno-UNUSEDSIGNAL` `-Wno-VARHIDDEN`.

-Wpedantic

  Warn on any construct demanded by IEEE, and disable all Verilator extensions that may interfere with IEEE compliance to the standard defined with `--default-language`, etc. Similar to gcc -Wpedantic. Rarely used, and intended only for strict compliance tests.

  This option changes `ASSIGNIN` from an error to a warning.

-Wwarn-<message>

  Enables the specified warning message.

-Wwarn-lint

  Enable all lint-related warning messages (note that by default, they are already enabled), but do not affect style messages. This is equivalent to `-Wwarn-ALWCOMBORDER` `-Wwarn-ASCRANGE` `-Wwarn-BSSPACE` `-Wwarn-CASEINCOMPLETE` `-Wwarn-CASEOVERLAP` `-Wwarn-CASEWITHX` `-Wwarn-CASEX` `-Wwarn-CASTCONST` `-Wwarn-CMPCONST` `-Wwarn-COLONPLUS` `-Wwarn-IMPLICIT` `-Wwarn-IMPLICITSTATIC` `-Wwarn-LATCH` `-Wwarn-MISINDENT` `-Wwarn-NEWERSTD` `-Wwarn-PINMISSING` `-Wwarn-REALCVT` `-Wwarn-STATICVAR` `-Wwarn-UNSIGNED` `-Wwarn-WIDTHTRUNC` `-Wwarn-WIDTHEXPAND` `-Wwarn-WIDTHXZEXPAND`.

-Wwarn-style

  Enable all code style-related warning messages. This is equivalent to `-Wwarn-ASSIGNDLY` `-Wwarn-DECLFILENAME` `-Wwarn-DEFPARAM` `-Wwarn-EOFNEWLINE` `-Wwarn-GENUNNAMED` `-Wwarn-INCABSPATH` `-Wwarn-PINNOCONNECT` `-Wwarn-SYNCASYNCNET` `-Wwarn-UNDRIVEN` `-Wwarn-UNUSEDGENVAR` `-Wwarn-UNUSEDPARAM` `-Wwarn-UNUSEDSIGNAL` `-Wwarn-VARHIDDEN`.

--x-assign 0

--x-assign 1

--x-assign fast (default)

--x-assign unique

  Controls the two-state value that is substituted when an explicit X value is encountered in the source. “–x-assign fast”, the default, converts all Xs to whatever is best for performance. “–x-assign 0” converts all Xs to 0s, and is also fast. “–x-assign 1” converts all Xs to 1s, this is nearly as fast as 0, but more likely to find reset bugs as active high logic will fire. Using “–x-assign unique” will result in all explicit Xs being replaced by a constant value determined at runtime. The value is determined by calling a function at initialization time. This enables the randomization of Xs with different seeds on different executions. This method is the slowest, but safest for finding reset bugs.

  If using “–x-assign unique”, you may want to seed your random number generator such that each regression run gets a different randomization sequence. The simplest is to use the `+verilator+seed+<value>` runtime option. Alternatively, use the system’s `srand48()` or for Windows `srand()` function to do this. You’ll probably also want to print any seeds selected, and code to enable rerunning with that same seed so you can reproduce bugs.

  Note

  This option applies only to values explicitly written as X in modules (not classes) in the Verilog source code. Initial values of clocks are set to 0 unless –x-initial-edge is specified. Initial values of all other state holding variables are controlled with –x-initial.

--x-initial 0

--x-initial fast

--x-initial unique (default)

  Controls the two-state value used to initialize variables that are not otherwise initialized.

  “–x-initial 0”,

    initializes all otherwise uninitialized variables to zero.

  “–x-initial unique”, the default,

    initializes variables using a function, which determines the value to use for each initialization. This gives the greatest flexibility and allows for finding reset bugs. See Unknown States.

  “–x-initial fast”,

    is best for performance, and initializes all variables to a state Verilator determines is optimal. This may allow further code optimizations, but will likely hide any code bugs relating to missing resets.

  Note

  This option applies only to the initial values of variables. Initial values of clocks are set to 0 unless `--x-initial-edge` is specified.

--x-initial-edge

  Enables emulation of event-driven simulators, which generally trigger an edge on a transition from X to 1 (posedge) or X to 0 (negedge). Thus the following code, where `rst_n` is uninitialized would set `res_n` to `1'b1` when `rst_n` is first set to zero:

      reg  res_n = 1'b0;

      always @(negedge rst_n) begin
         if (rst_n == 1'b0) begin
            res_n <= 1'b1;
         end
      end

  In Verilator, by default, uninitialized clocks are given a value of zero, so the above `always` block would not trigger.

  While it is not good practice, some designs rely on X->0 triggering a negedge, particularly in reset sequences. Using `--x-initial-edge` will replicate this behavior. It will also ensure that X->1 triggers a posedge.

  Note

  Using this option can affect convergence, and it may be necessary to use `--converge-limit` to increase the number of convergence iterations. This may be another indication of problems with the modeled design that should be addressed.

--xml-only

  Create XML output only, do not create any other output.

  The XML format is intended to be used to leverage Verilator’s parser and elaboration to feed to other downstream tools. Be aware that the XML format is still evolving; there will be some changes in future versions.

--xml-output <filename>

  Specifies the filename for the XML output file. Using this option automatically sets `--xml-only`.

-y <dir>

  Add the directory to the list of directories that should be searched to find include files or libraries. The three flags `-y`, `+incdir+<dir>` and `-I<dir>` have a similar effect; `+incdir+<dir>` and `-y` are relatively standard across Verilog tools while `-I<dir>` is used by many C++ compilers.

  Verilator defaults to the current directory “-y .” and any specified `--Mdir`, though these default paths are used after any user-specified directories. This allows ‘-y “$(pwd)”’ to be used if absolute filenames are desired for error messages instead of relative filenames.

# Configuration Files

In addition to the command line, warnings and other features for the verilator command may be controlled with configuration files, typically named with the .vlt extension (what makes it a configuration file is the ``verilator_config` directive). An example:

    `verilator_config
    lint_off -rule WIDTH
    lint_off -rule CASEX  -file "silly_vendor_code.v"

This disables WIDTH warnings globally, and CASEX for a specific file.

Configuration files are fed through the normal Verilog preprocessor prior to parsing, so “`ifdef”, “`define”, and comments may be used as if the configuration file was standard Verilog code.

Note that file or line-specific configuration only applies to files read after the configuration file. It is therefore recommended to pass the configuration file to Verilator as the first file.

The grammar of configuration commands is as follows:

`verilator_config

  Take the remaining text and treat it as Verilator configuration commands.

coverage_on [-file "<filename>" [-lines <line> [ - <line> ]]]

coverage_off [-file "<filename>" [-lines <line> [ - <line> ]]]

  Enable/disable coverage for the specified filename (or wildcard with ‘*’ or ‘?’, or all files if omitted) and range of line numbers (or all lines if omitted). Often used to ignore an entire module for coverage analysis purposes.

clock_enable -module "<modulename>" -var "<signame>"

  Deprecated and has no effect (ignored).

  In versions before 5.000:

  Indicates that the signal is used to gate a clock, and the user takes responsibility for ensuring there are no races related to it.

  Same as `/*verilator clock_enable*/` metacomment.

clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"

clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"

no_clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"

no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"

  Indicates whether the signal is used as clock or not. Verilator uses this information to mark the signal and any derived signals as clocker. See `--clk`.

  Same as `/*verilator clocker*/` metacomment.

coverage_block_off -module "<modulename>" -block "<blockname>"

coverage_block_off -file "<filename>" -line <lineno>

  Specifies the entire begin/end block should be ignored for coverage analysis purposes. It can either be specified as a named block or as a filename and line number.

  Same as `/*verilator coverage_block_off*/` metacomment.

forceable -module "<modulename>" -var "<signame>"

  Generate public <signame>__VforceEn and <signame>__VforceVal signals that can force/release a signal from C++ code. The force control signals are created as `public_flat` signals.

  Same as `/*verilator forceable*/` metacomment.

full_case -file "<filename>" -lines <lineno>

parallel_case -file "<filename>" -lines <lineno>

  Same as `//synopsys full_case` and `//synopsys parallel_case`. When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or, failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an “Assertion failed” error message.

hier_block -module "<modulename>"

  Specifies that the module is an unit of hierarchical Verilation. Note that the setting is ignored unless the `--hierarchical` option is specified. See Hierarchical Verilation.

inline -module "<modulename>"

  Specifies the module may be inlined into any modules that use this module. Same as `/*verilator inline_module*/` metacomment.

isolate_assignments -module "<modulename>" [-task "<taskname>"] -var "<signame>"

isolate_assignments -module "<modulename>" [-function "<funcname>"] -var "<signame>"

isolate_assignments -module "<modulename>" -function "<fname>"

  Used to indicate that the assignments to this signal in any blocks should be isolated into new blocks. Same as `/*verilator isolate_assignments*/` metacomment.

no_inline -module "<modulename>"

  Specifies the module should not be inlined into any modules that use this module. Same as `/*verilator no_inline_module*/` metacomment.

no_inline [-module "<modulename>"] -task "<taskname>"

no_inline [-module "<modulename>"] -function "<funcname>"

  Specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself.

  Same as `/*verilator no_inline_task*/` metacomment.

lint_on [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]

lint_off [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]

lint_off [-rule <message>] [-file "<filename>"] [-match "<string>"]

  Enable/disables the specified lint warning, in the specified filename (or wildcard with ‘*’ or ‘?’, or all files if omitted) and range of line numbers (or all lines if omitted).

  With lint_off using “*” will override any lint_on directives in the source, i.e. the warning will still not be printed.

  If the -rule is omitted, all lint warnings (see list in `-Wno-lint`) are enabled/disabled. This will override all later lint warning enables for the specified region.

  If -match is set, the linter warnings are matched against this (wildcard) string and are waived in case they match, provided with the rule and file also match.

  In previous versions -rule was named -msg. The latter is deprecated, but still works with a deprecation info; it may be removed in future versions.

public [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>"

public_flat [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>"

public_flat_rd [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>"

public_flat_rw [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>" "@(edge)"

  Sets the variable to be public. Same as `/*verilator public*/` or `/*verilator public_flat*/`, etc., metacomments. See also VPI Example.

profile_data -mtask "<mtask_hash>" -cost <cost_value>

  Feeds profile-guided optimization data into the Verilator algorithms in order to improve model runtime performance. This option is not expected to be used by users directly. See Thread Profile-Guided Optimization.

sc_bv -module "<modulename>" [-task "<taskname>"] -var "<signame>"

sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>"

  Sets the port to be of `sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t. Same as `/*verilator sc_bv*/` metacomment.

sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"

sformat [-module "<modulename>"] [-function "<funcname>"] -var "<signame>"

  Must be applied to the final argument of type `input string` of a function or task to indicate that the function or task should pass all remaining arguments through $sformatf. This allows the creation of DPI functions with $display-like behavior. See the `test_regress/t/t_dpi_display.v` file for an example.

  Same as `/*verilator sformat*/` metacomment.

split_var [-module "<modulename>"] [-task "<taskname>"] -var "<varname>"

split_var [-module "<modulename>"] [-function "<funcname>"] -var "<varname>"

  Break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself; see `UNOPTFLAT`.

  Same as `/*verilator split_var*/` metacomment.

timing_on [-file "<filename>" [-lines <line> [ - <line>]]]

timing_off [-file "<filename>" [-lines <line> [ - <line>]]]

  Enables/disables timing constructs for the specified file and lines. When disabled, all timing control constructs in the specified source code locations are ignored the same way as with the `--no-timing`, and code:fork/`join*` blocks are converted into `begin`/`end` blocks.

  Same as `/*verilator timing_on*/`, `/*verilator timing_off*/` metacomments.

tracing_on [-file "<filename>" [-lines <line> [ - <line> ]]]

tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]

tracing_on [-scope "<scopename>" [-levels <levels> ]]

tracing_off [-scope "<scopename>" [-levels <levels> ]]

  Enable/disable waveform tracing for all future signals declared in all files.

  With -file, enable/disable waveform tracing in the specified filename (or wildcard with ‘*’ or ‘?’), and -line range of line numbers (or all lines if omitted).

  For tracing_off with -file, instances below any module in the files/ranges specified will also not be traced. To overcome this feature, use tracing_on on the upper module declaration and on any cells, or use the -scope flavor of the command.

  With -scope enable/disable waveform tracing for the specified scope (or wildcard with ‘*’ or ‘?’), and optional –levels number of levels below. These controls only operate after other file/line/module-based controls have indicated the signal should be traced.

  With -levels (used with -scope), the number of levels below that scope which the rule is to match, where 0 means all levels below, 1 the exact level as the provided scope, and 2 means an additional level of children below the provided scope, etc.