Loading...
Searching...
No Matches
FPGA Manual

Welcome to the USRP FPGA HDL source code tree! This repository contains free & open-source FPGA HDL for the Universal Software Radio Peripheral (USRP™) SDR platform, created and sold by Ettus Research. A large percentage of the source code is written in Verilog.

# Product Generations

This repository contains the FPGA source for the following generations of USRP devices.

## Generation 1

- Directory: usrp1
- Devices: USRP Classic Only
- Tools: Quartus from Altera
- Build Instructions

## Generation 2

- Directory: usrp2
- Devices: USRP N2X0, USRP B100, USRP E1X0, USRP2
- Tools: ISE from Xilinx, GNU make
- Build Instructions
- Customization Instructions

## Generation 3

- Directory: usrp3
- Devices: USRP B2XX, USRP E3XX, USRP N3XX, USRP X3XX, USRP X4XX
- Tools: Vivado/ISE from Xilinx, GNU make
- Build Instructions
- Simulation Instructions

# Pre-built FPGA Images

Pre-built FPGA and Firmware images are not hosted here. Please visit Firmware and FPGA Images for instructions on downloading and using pre-built images. In most cases, running

    $ uhd_images_downloader

will do the right thing.