# [−][src]Function core::arch::mips64::__msa_srlr_d

    pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64

🔬 This is a nightly-only experimental API. (`stdsimd` #48556)
This is supported on MIPS-64 and target feature `msa` only.

Vector Shift Right Logical Rounded

The elements in vector `a` (two signed 64-bit integer numbers) are shifted right logical by the number of bits the elements in vector `b` (two signed 64-bit integer numbers) specify modulo the size of the element in bits.The most significant discarded bit is added to the shifted value (for rounding) and the result is written to vector (two signed 64-bit integer numbers).