# [−][src]Function core::arch::mips::__msa_srl_h

    pub unsafe fn __msa_srl_h(a: v8i16, b: v8i16) -> v8i16

🔬 This is a nightly-only experimental API. (`stdsimd` #48556)
This is supported on MIPS and target feature `msa` only.

Vector Shift Right Logical

The elements in vector `a` (eight signed 16-bit integer numbers) are shifted right logical by the number of bits the elements in vector `b` (eight signed 16-bit integer numbers) specify modulo the size of the element in bits.The result is written to vector (eight signed 16-bit integer numbers).