# [−][src]Function core::arch::arm::__ISB

    pub unsafe fn __ISB()

🔬 This is a nightly-only experimental API. (`stdsimd` #48556)
This is supported on ARM and target feature `mclass` only.

Instruction Synchronization Barrier

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

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