# pyuvm package

## Submodules

## pyuvm.error_classes module

exception pyuvm.error_classes.UVMBadPhase

  Bases: `UVMError`

  Errors in phasing

exception pyuvm.error_classes.UVMConfigError

  Bases: `UVMError`

  Errors using the config_db

exception pyuvm.error_classes.UVMConfigItemNotFound

  Bases: `UVMError`

  Couldn’t find something in config_db

exception pyuvm.error_classes.UVMError

  Bases: `Exception`

  All UVM Errors

exception pyuvm.error_classes.UVMFactoryError

  Bases: `UVMError`

  For cases where a type is not registered with the factory

exception pyuvm.error_classes.UVMFatalError

  Bases: `UVMError`

  Used to dump out of the testbench

exception pyuvm.error_classes.UVMNotImplemented

  Bases: `UVMError`

  For methods that we haven’t yet implemented.

exception pyuvm.error_classes.UVMSequenceError

  Bases: `UVMError`

  Errors using sequences

exception pyuvm.error_classes.UVMTLMConnectionError

  Bases: `UVMError`

  For problems connecting TLM

exception pyuvm.error_classes.UsePythonMethod

  Bases: `UVMError`

  For cases where the user should use a Python method rather than a UVM method.

## pyuvm.extension_classes module

pyuvm.extension_classes.test(timeout_time=None, timeout_unit='step', expect_fail=False, expect_error=(), skip=False, stage=None, keep_singletons=False, keep_set={})

## pyuvm.s05_base_classes module

This file defines the UVM base classes

class pyuvm.s05_base_classes.uvm_field_op(*args, **kwargs)

  Bases: `object`

  We do not implement the UVM field op as this is a UVM way of providing field-based functionality that can better be implemented using Python functionality.

class pyuvm.s05_base_classes.uvm_object(name='')

  Bases: `uvm_void`

  The most basic UVM object

  clone()
    Returns:

      A new object with the same name and data as this object.

  compare(rhs)
    Parameters:

      rhs – The object being compared.

    Returns:

      True if do_compare() believes the objects are the same.

    Compares one uvm_object to another uvm_object using the user-overridden `do_compare()` function.

  convert2string()
    Returns:

      The result of `__str__()`

    Override if you want something different than `__str__()`

  copy(rhs)
    Parameters:

      rhs – The object to copy from

    Returns:

      None

    Copy fields from rhs to this object using `self.do_copy()`

  classmethod create(name)
    Returns:

      new object from factory

  do_compare(rhs)
    Parameters:

      rhs – The object being compared.

    Returns:

      True if the objects are the same.

    Uses `__eq__()` to compare the objects. Override this to change the compare behavior.

  do_copy(rhs)
    Parameters:

      rhs – The object to copy from

    Returns:

      None

    By default we copy the name. Override this function to copy the rest of the object members.

  do_execute_op(op)

    Not implemented.

  do_pack()

    Not implemented. There are Pythonic solutions to this.

  do_print()

    not implemented. Use __str__() and print()

  do_record()

    Not implemented as we are not in a simulator

  do_unpack()

    Not implemented. There are Pythonic solutions to this.

  get_active_policy()

    Not implemented.

  get_full_name()
    Returns:

      The full path and name of the object

    The full name for a uvm_object is simply the name

  get_inst_id()
    Returns:

      The python ID which fits the bill for what the ID is supposed to be.

  get_name()
    Returns:

      String with name of uvm_object.

    Return the name of this object as passed by the constructor

  get_object_type()

    Not implemented because Python can implement the factory without these shenanigans.

  get_type()

    Not implemented because Python can implement the factory without these shenanigans.

  get_type_name()
    Returns:

      Returns the type’s `__name__` magic variable

  get_uvm_seeding()

    Not implemented

  pack()

    Not implemented. There are Pythonic solutions to this.

  pack_bytes()

    Not implemented. There are Pythonic solutions to this.

  pack_ints()

    Not implemented. There are Pythonic solutions to this.

  pack_longints()

    Not implemented. There are Pythonic solutions to this.

  pop_active_policy()

    Not implemented.

  print()

    Not implemented. Use __str__() and print()

  push_active_policy()

    Not implemented.

  record()

    Not implemented.

  reseed()

    Not implemented

  set_local()

    Not implemented use Python getattr and setattr.

  set_name(name)
    Parameters:

      name – Name of the object

    Set the name

  set_uvm_seeding(enable)

    Not implemented

  sprint()

    Not implemented. use __str__() and print()

  unpack()

    Not implemented. There are Pythonic solutions to this.

  unpack_bytes()

    Not implemented. There are Pythonic solutions to this.

  unpack_ints()

    Not implemented. There are Pythonic solutions to this.

  unpack_longints()

    Not implemented. There are Pythonic solutions to this.

class pyuvm.s05_base_classes.uvm_policy(*args, **kwargs)

  Bases: `object`

  The uvm_policy is used to add functionality to SystemVerilog that already exists in Python. It is not needed in pyuvm.

class pyuvm.s05_base_classes.uvm_transaction(name='', initiator=None)

  Bases: `uvm_object`

  Transactions without interface to logging or waveforms.

  accept_tr(accept_time=0)
    Parameters:

      accept_time – Simulation time when the transaction is accepted

    IEEE 1800.2 5.4.2.2

  begin_tr(begin_time=0, parent_handle=None) → int
    Parameters:

      - begin_time – Simulation time at which the transaction is acted upon by the driver

      - parent_handle

  disable_recording()

    Not implemented

  do_accept_tr()

    User definable method to add to `accept_tr()`

  do_begin_tr()

    User definable method

  do_end_tr()

    Not implemented

  enable_recording()

    Not implemented

  end_tr(end_time=0, free_handle=True) → None
    Parameters:

      - end_time – Simulation time at which the transaction is marked as acted upon

      - free_handle

    Returns:

      None

  get_accept_time() → int
    Returns:

      Accept time of transaction

  get_begin_time() → int
    Returns:

      Begin time of transaction

  get_end_time() → int
    Returns:

      End time of transaction

  get_event_pool()

    Not implemented

  get_initiator()
    Returns:

      initiator

    5.4.2.15

  get_tr_handle()

    Not implemented

  get_transaction_id()
    Returns:

      Transaction ID

    Returns transaction_id

  is_active()

    Not implemented

  is_recording_enabled()

    Not implemented

  set_id_info(other)
    Parameters:

      other – uvm_transaction with transaction_id

    Returns:

      None

    Set transaction_id from other

  set_initiator(initiator)
    Parameters:

      initiator – initiator to set

    Returns:

      None

    5.4.2.14

  set_transaction_id(txn_id)
    Parameters:

      txn_id – Transaction ID

    Sets transaction’s transaction_id

## pyuvm.s06_reporting_classes module

class pyuvm.s06_reporting_classes.PyuvmFormatter(full_name)

  Bases: `SimLogFormatter`

  format(record)
    Parameters:

      record – The log record

class pyuvm.s06_reporting_classes.uvm_report_object(name)

  Bases: `uvm_object`

  add_logging_handler(handler)
    Parameters:

      handler – The logging handler

    Returns:

      None

  disable_logging()
    Returns:

      None

    Disables logging

  static get_default_logging_level()
    Returns:

      The default logging level

  get_initial_logger_name()
    Returns:

      The name of the initial logger

    Override this method if you want to change the way the logger name is generated.

    The default looks like this:

  remove_logging_handler(handler)
    Parameters:

      handler – The logging handler to remove

    Returns:

      None

  remove_streaming_handler()
    Returns:

      None

    Removes the streaming handler

  static set_default_logging_level(default_logging_level)
    Parameters:

      default_logging_level – The default logging level

    Returns:

      None

  set_logging_level(logging_level)
    Parameters:

      logging_level – The logging level

    Returns:

      None

## pyuvm.s08_factory_classes module

class pyuvm.s08_factory_classes.uvm_factory(*args, **kwargs)

  Bases: `object`

  The uvm_factory is a singleton that delivers all UVM factory functions.

  clear_all()

    Clear all the classes and overrides from the factory

  clear_overrides()

    Clear all the overrides from the factory

  create_component_by_name(requested_type_name, parent_inst_path='', name='', parent=None)

    Create a components using the name of the requested uvm_component type

    Parameters:

      - requested_type_name – the type that could be overridden

      - parent_inst_path – A path if we are checking for inst overrides

      - name – The name of the new object.

      - parent – The component’s parent component

    Raises:

      UVMFactoryError if the type is not in the factory

    Returns:

      A uvm_object with the name given

  create_component_by_type(requested_type, parent_inst_path='', name='', parent=None)
    Parameters:

      - requested_type – Type type to be overridden

      - parent_inst_path – The inst path if we are looking for inst overrides

      - name – Concatenated with parent_inst_path if it exists for inst overrides

      - parent – The parent component

    Raises:

      UVMFactoryError if the type is not in the factory

    Returns:

      a uvm_component with the name an parent given.

    Create a component of the requested uvm_component type. If the type is is not in the factory we raise UVMFactoryError

  create_object_by_name(requested_type_name, parent_inst_path='', name='')
    Parameters:

      - requested_type_name – the type that could be overridden

      - parent_inst_path – A path if we are checking for inst overrides

      - name – The name of the new object.

    Raises:

      UVMFactoryError if the type is not in the factory

    Returns:

      A uvm_object with the name given

    Create an object using a string to define its uvm_object type.

  create_object_by_type(requested_type, parent_inst_path='', name='')
    Parameters:

      - requested_type – The type that we request but that can be overridden

      - parent_inst_path – The get_full_name path of the parent

      - name – The name of the instance requested_type(“name”)

    Raises:

      UVMFactoryError if the type is not in the factory

    Returns:

      Type that is child of uvm_object.

    8.3.1.5 Creation If the type is is not in the factory we raise UVMFactoryError

  property debug_level

    - uvm_factory().debug_level = 0 : overrides

    - uvm_factory().debug_level = 1 : user defined types + above

    - uvm_factory().debug_level = 2 : uvm_* types + above

  find_override_by_name(requested_type_name, full_inst_path)
    Parameters:

      - requested_type_name

      - full_inst_path

    Raises:

      UVMFactoryError if the type is not in the factory

    Returns:

      class object

    Given a path and the name of a class return its overriding class object

  find_override_by_type(requested_type, full_inst_path)
    Parameters:

      - requested_type – The type whose override you want

      - full_inst_path – The inst path where one looks

    Raises:

      UVMFactoryError if the type is not in the factory

    Returns:

      class object

    Given a type and instance path, return the override class object.

  find_wrapper_by_name()
    Raises:

      UVMNotImplemented There are no wrappers in pyuvm so this is not implemented.

  is_type_name_registered(type_name)
    Parameters:

      type_name – string that is name of a type

    Returns:

      boolean True if type is registered

    Checks that a type of this name is registered with the factory.

  is_type_registered(uvm_type)
    Parameters:

      uvm_type – The type to be checked

    Returns:

      boolean True if type is registered

    Checks that a type is registered. The argument is named “obj” in the spec, but that name is ridiculous and confusing.

  print(debug_level=1)
    Parameters:

      debug_level –

      - `debug_level` = 0 : overrides

      - `debug_level` = 1 : user defined types + above ( default)

      - `debug_level` = 2 : uvm_* types + above

    Returns:

      None

    Prints the factory data using debug_level to control the amount of output. The uvm_factory().debug_level variable can control this for __str__()

  set_inst_alias(alias_type_name, original_type, full_inst_path)

    :param alias_type_name:A string that will reference the original type :param original_type:The original type toe be referenced :param full_inst_path: The instance path where this alias is active :raises: UVMNotImplemented Not implemented as it does

    > not seem to exist in SystemVerilog UVM

    :return:None

  set_inst_override_by_name(original_type_name, override_type_name, full_inst_path)
    Parameters:

      - original_type_name – the name of type being replaced

      - override_type_name – the name of the substitute type

      - full_inst_path – The path to the instance

    Returns:

      None

    Override a specific instance using strings that contain the names of the types.

  set_inst_override_by_type(original_type, override_type, full_inst_path)
    Parameters:

      - original_type – The original type being overridden

      - override_type – The overriding type

      - full_inst_path – The inst where this happens

    Returns:

      None

    Override an instance with a new type if original type is at that path

  set_type_alias(alias_type_name, original_type)

    :param alias_type_name:A string that will reference the original type :param original_type:The original type toe be referenced :raises: UVMNotImplemented Not implemented as it does not seem to exist in the SystemVerilog UVM :return:None

  set_type_override_by_name(original_type_name, override_type_name, replace=True)
    Parameters:

      - original_type_name – The name of the type to be overridden or an arbitrary string.

      - override_type_name – The name of the overriding type. It must have been declared.

      - replace – If the override already exists only replace if this is True

    Override one type with another type globally using strings containing the type names.

  set_type_override_by_type(original_type, override_type, replace=True)
    Parameters:

      - original_type – The original type to be overridden

      - override_type – The new type that will override it

      - replace – If the override exists, only replace it if this is True

    Returns:

      None

    Override one type with another type globally

## pyuvm.s09_phasing module

class pyuvm.s09_phasing.uvm_bottomup_phase(name='')

  Bases: `uvm_phase`

  Runs the phases from bottom up.

  classmethod traverse(comp)
    Parameters:

      comp – The component whose hierarchy will be traversed

    Given a component, we traverse the component tree bottom to top calling the phase functions as we go

class pyuvm.s09_phasing.uvm_build_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_check_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_connect_phase(name='')

  Bases: `uvm_bottomup_phase`

class pyuvm.s09_phasing.uvm_end_of_elaboration_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_extract_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_final_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_phase(name='')

  Bases: `uvm_object`

  classmethod execute(comp)
    Parameters:

      comp – The component whose turn it is to execute

class pyuvm.s09_phasing.uvm_report_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_run_phase(name='')

  Bases: `uvm_threaded_execute_phase`, `uvm_bottomup_phase`

class pyuvm.s09_phasing.uvm_start_of_simulation_phase(name='')

  Bases: `uvm_topdown_phase`

class pyuvm.s09_phasing.uvm_threaded_execute_phase(name='')

  Bases: `uvm_phase`

  This phase launches the phase function in a thread and returns the thread to the caller. The caller can then join all the threads.

  classmethod execute(comp)
    Parameters:

      comp – The component whose turn it is to execute

class pyuvm.s09_phasing.uvm_topdown_phase(name='')

  Bases: `uvm_phase`

  Runs phases from the top down.

  classmethod traverse(comp)
    Parameters:

      comp – The component whose hierarchy will be traversed

    Given a component, we traverse the component tree top to bottom calling the phase functions as we go

## pyuvm.s12_uvm_tlm_interfaces module

class pyuvm.s12_uvm_tlm_interfaces.uvm_QueueAccessor(name, parent, uvm_queue, ap)

  Bases: `object`

class pyuvm.s12_uvm_tlm_interfaces.uvm_analysis_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_analysis_port(name, parent)

  Bases: `uvm_port_base`

  connect(export)
    Parameters:

      export – The export that has the functions

    Raises:

      UVMTLMConnectionError if there is a connect error

    Returns:

      None

    Attach this port to the associated export.

  write(datum)

    Write to all connected analysis ports. This is a broadcast. Returns regardless of whether there are any subscribers.

    Parameters:

      datum – data to send

    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      None

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_get_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port(name, parent)

  Bases: `uvm_blocking_get_port`, `uvm_blocking_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_get_port(name, parent)

  Bases: `uvm_port_base`

  Access the blocking get export methods

  async get()
    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      data

    A blocking get that returns the data got

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_master_export(name, parent)

  Bases: `uvm_blocking_put_export`, `uvm_blocking_get_peek_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_master_port(name, parent)

  Bases: `uvm_blocking_put_port`, `uvm_blocking_get_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_peek_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_peek_port(name, parent)

  Bases: `uvm_port_base`

  Provides access to the peek methods

  async peek()
    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      datum

    A blocking peek that returns data without consuming it.

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_put_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_put_port(name, parent)

  Bases: `uvm_port_base`

  Access the blocking put interfaces

  async put(datum)

    > param datum:

    >   Datum to put

    > raises:

    >   UVMTLMConnectionError if export is missing

    > return:

    >   None

    put the datum

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_slave_export(name, parent)

  Bases: `uvm_blocking_put_export`, `uvm_blocking_get_peek_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_slave_port(name, parent)

  Bases: `uvm_blocking_put_port`, `uvm_blocking_get_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_transport_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_blocking_transport_port(name, parent)

  Bases: `uvm_port_base`

  async transport(put_data)

    Puts data and blocks if there is no room, then blocks if there is no data to get and gets data.

    Parameters:

      put_data – data to send

    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      data received

class pyuvm.s12_uvm_tlm_interfaces.uvm_export_base(name, parent)

  Bases: `uvm_component`

class pyuvm.s12_uvm_tlm_interfaces.uvm_get_export(name, parent)

  Bases: `uvm_blocking_get_export`, `uvm_nonblocking_get_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_get_peek_export(name, parent)

  Bases: `uvm_nonblocking_get_peek_export`, `uvm_blocking_get_peek_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_get_peek_port(name, parent)

  Bases: `uvm_blocking_get_peek_port`, `uvm_nonblocking_get_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_get_port(name, parent)

  Bases: `uvm_blocking_get_port`, `uvm_nonblocking_get_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_master_export(name, parent)

  Bases: `uvm_blocking_master_export`, `uvm_nonblocking_master_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_master_port(name, parent)

  Bases: `uvm_blocking_master_port`, `uvm_nonblocking_master_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_get_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port(name, parent)

  Bases: `uvm_nonblocking_get_port`, `uvm_nonblocking_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_get_port(name, parent)

  Bases: `uvm_port_base`

  Access the non_blocking methods in export

  can_get()
    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      bool Returns true if there is data to get

  try_get()
    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      (success, data)

    12.2.4.2.6 Returns a tuple containing success and the data This is different than SV UVM that returns the data through the argument list. :return: (success, data)

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_master_export(name, parent)

  Bases: `uvm_blocking_peek_export`, `uvm_nonblocking_get_peek_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_master_port(name, parent)

  Bases: `uvm_nonblocking_put_port`, `uvm_nonblocking_get_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_peek_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_peek_port(name, parent)

  Bases: `uvm_port_base`

  Try a peek

  can_peek()
    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      True if can peek

    Checks if peeking will be successful

  try_peek()
    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      (success, data)

    Tries to peek for data and returns a tuple with success and the data

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_put_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_put_port(name, parent)

  Bases: `uvm_port_base`

  Access the non_blocking put interface

  can_put()

    Returns true if there is room for data to be put on the port

    Returns:

      True if there is room to put

  try_put(data)
    Parameters:

      data – data to deliver

    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      boolean True = success

    Tries to put data on a port, but if the port is full it returns False

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_slave_export(name, parent)

  Bases: `uvm_nonblocking_put_export`, `uvm_nonblocking_get_peek_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_slave_port(name, parent)

  Bases: `uvm_nonblocking_get_peek_port`, `uvm_nonblocking_put_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_transport_export(name, parent)

  Bases: `uvm_export_base`

class pyuvm.s12_uvm_tlm_interfaces.uvm_nonblocking_transport_port(name, parent)

  Bases: `uvm_port_base`

  nb_transport(put_data)

    Non-blocking transport. Returns a tuple with success if the transport was successful and the data could be returned

    Parameters:

      put_data – data to send

    Raises:

      UVMTLMConnectionError if export is missing

    Returns:

      (success, data)

class pyuvm.s12_uvm_tlm_interfaces.uvm_peek_export(name, parent)

  Bases: `uvm_nonblocking_peek_export`, `uvm_blocking_peek_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_peek_port(name, parent)

  Bases: `uvm_blocking_peek_port`, `uvm_nonblocking_peek_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_port_base(name, parent)

  Bases: `uvm_export_base`

  A `uvm_port_base` is a uvm_component with a `connect()` function. The `connect` function creates an `__export` data member that implements the put/get,etc methods.

  We’ll build functionality from `uvm_port_base` to create the other combinations of ports through multiple inheritance.

  pyuvm will make extensive use of Pythons “ask forgiveness” policy If you try to use the wrong method for the port you created then you’ll get a exception, maybe a missing attribute exception, though we could catch that one and deliver a more useful message.

  Unlike the SV implementation of UVM we return results from get and peek as function call returns. This is more pythonic.

  connect(export)
    Parameters:

      export – The export that has the functions

    Raises:

      UVMTLMConnectionError if there is a connect error

    Returns:

      None

    Attach this port to the associated export.

class pyuvm.s12_uvm_tlm_interfaces.uvm_put_export(name, parent)

  Bases: `uvm_nonblocking_put_export`, `uvm_blocking_put_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_put_port(name, parent)

  Bases: `uvm_blocking_put_port`, `uvm_nonblocking_put_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_slave_export(name, parent)

  Bases: `uvm_blocking_slave_export`, `uvm_nonblocking_slave_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_slave_port(name, parent)

  Bases: `uvm_nonblocking_slave_port`, `uvm_blocking_slave_port`

class pyuvm.s12_uvm_tlm_interfaces.uvm_tlm_analysis_fifo(name, parent=None)

  Bases: `uvm_tlm_fifo`

  class uvm_AnalysisExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_analysis_port`

    write(item)
      Parameters:

        item – item to write

      Writes the item to all the subscribers, or no one if there are no subscribers.

class pyuvm.s12_uvm_tlm_interfaces.uvm_tlm_fifo(name=None, parent=None, size=1)

  Bases: `uvm_tlm_fifo_base`

  flush()

    Flush out the FIFO

  is_empty()

    Returns true if FIFO is empty

    Returns:

      True if empty

  is_full()

    Test for full FIFO

    Returns:

      True if full

  size()
    Returns:

      size of FIFO

    Return the size of the fifo

  used()
    Returns:

      Number of items in the FIFO

    How much of the FIFO is being used?

class pyuvm.s12_uvm_tlm_interfaces.uvm_tlm_fifo_base(name, parent, maxsize=1)

  Bases: `uvm_component`

  Declares and instantiate the exports needed to communicate through the Queue.

  can_get()
    Returns:

      True if can get

  can_peek()
    Returns:

      True if can peek

  can_put()
    Returns:

      True if can put

  async get()
    Returns:

      item

    coroutine that blocks if FIFO is empty

  async peek()
    Returns:

      item

    A coroutine that blocks if FIFO is empty

  async put(item)
    Parameters:

      item – item to put

    Blocking put coroutine

  try_get()
    Returns:

      (success, item)

  try_peek()
    Returns:

      (success, item)

  try_put(item)
    Parameters:

      item – item to put

    Returns:

      True if successful

  class uvm_BlockingGetExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_blocking_get_export`

    async get()
      Returns:

        item

      A coroutine that blocks if the FIFO is empty

  class uvm_BlockingGetPeekExport(name, parent, uvm_queue, ap)

    Bases: `uvm_BlockingGetExport`, `uvm_BlockingPeekExport`

  class uvm_BlockingPeekExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_blocking_peek_export`

    async peek()
      Returns:

        item

      A coroutine that blocks if the FIFO is empty

  class uvm_BlockingPutExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_blocking_put_export`

    async put(item)
      Parameters:

        item – item to put

      Returns:

        None

      A coroutine that blocks if the FIFO is full.

  class uvm_GetExport(name, parent, uvm_queue, ap)

    Bases: `uvm_BlockingGetExport`, `uvm_NonBlockingGetExport`

  class uvm_GetPeekExport(name, parent, uvm_queue, ap)

    Bases: `uvm_GetExport`, `uvm_PeekExport`

  class uvm_NonBlockingGetExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_nonblocking_get_export`

    can_get()
      Returns:

        True if can get

    try_get()
      Returns:

        (success, item)

  class uvm_NonBlockingGetPeekExport(name, parent, uvm_queue, ap)

    Bases: `uvm_NonBlockingGetExport`, `uvm_NonBlockingPeekExport`

  class uvm_NonBlockingPeekExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_nonblocking_peek_export`

    can_peek()
      Returns:

        True if can peek

    try_peek()
      Returns:

        (success, item)

  class uvm_NonBlockingPutExport(name, parent, uvm_queue, ap)

    Bases: `uvm_QueueAccessor`, `uvm_nonblocking_put_export`

    can_put()
      Returns:

        True if can put

    try_put(item)
      Parameters:

        item – item to put

      Raises:

        QueueFull if the queue is full

      Returns:

        True if successful

      The `try_put` is implemented with an exception rather than returning a boolean.

  class uvm_PeekExport(name, parent, uvm_queue, ap)

    Bases: `uvm_BlockingPeekExport`, `uvm_NonBlockingPeekExport`

  class uvm_PutExport(name, parent, uvm_queue, ap)

    Bases: `uvm_BlockingPutExport`, `uvm_NonBlockingPutExport`

class pyuvm.s12_uvm_tlm_interfaces.uvm_tlm_req_rsp_channel(name, parent=None, request_fifo_size=1, response_fifo_size=1)

  Bases: `uvm_component`

  connect_phase()
  class uvm_MasterSlaveExport(name, parent, put_export, get_peek_export)

    Bases: `uvm_master_port`, `uvm_get_peek_port`

    can_get()
      Returns:

        True if can get

    can_put()
      Returns:

        True if can put

    async get()
      Returns:

        item

      A coroutine that blocks if the FIFO is empty

    async put(item)
      Parameters:

        item – item to put

      A coroutine that blocks if the FIFO is full

    try_get()
      Returns:

        (success, item)

    try_put(item)
      Parameters:

        item – item to put

      Returns:

        True if successful

class pyuvm.s12_uvm_tlm_interfaces.uvm_tlm_transport_channel(name, parent=None)

  Bases: `uvm_tlm_req_rsp_channel`

  class uvm_TransportExport(name, parent, req_fifo, rsp_fifo)

    Bases: `uvm_transport_port`

    nb_transport(req)

      Non-blocking transport. Returns a tuple with success if the transport was successful and the data could be returned

      Parameters:

        put_data – data to send

      Raises:

        UVMTLMConnectionError if export is missing

      Returns:

        (success, data)

    async transport(req)

      Puts data and blocks if there is no room, then blocks if there is no data to get and gets data.

      Parameters:

        put_data – data to send

      Raises:

        UVMTLMConnectionError if export is missing

      Returns:

        data received

class pyuvm.s12_uvm_tlm_interfaces.uvm_transport_export(name, parent)

  Bases: `uvm_nonblocking_transport_export`, `uvm_blocking_transport_export`

class pyuvm.s12_uvm_tlm_interfaces.uvm_transport_port(name, parent)

  Bases: `uvm_blocking_transport_port`, `uvm_nonblocking_transport_port`

## pyuvm.s13_predefined_component_classes module

class pyuvm.s13_predefined_component_classes.uvm_active_passive_enum(*values)

  Bases: `IntEnum`

  UVM_ACTIVE = 1
  UVM_PASSIVE = 0

class pyuvm.s13_predefined_component_classes.uvm_agent(name, parent)

  Bases: `uvm_component`

  The `uvm_agent` virtual class should be used as the base class for the user-defined agents. Deriving from `uvm_agent` will allow you to distinguish agents from other component types also using its inheritance. Such agents will automatically inherit features that may be added to `uvm_agent` in the future.

  While an agent’s build function, inherited from `uvm_component`, can be implemented to define any agent topology, an agent typically contains three subcomponents: a driver, sequencer, and monitor. If the agent is active, subtypes should contain all three subcomponents. If the agent is passive, subtypes should contain only the monitor.

  active()
  build_phase()
    This `build_phase()` implements agent-specific behavior.

      - It sets the agent’s `is_active` property to `UVM_ACTIVE`

      - It allows the user to override the `is_active` property using the `cdb_get()` method.

      - It logs a warning if the user sets an illegal value for `is_active` and sets the value to `UVM_ACTIVE`.

  get_is_active()

    Returns `UVM_ACTIVE` if the agent is acting as an active agent and `UVM_PASSIVE` if it is acting as a passive agent. The default implementation is to just return the `is_active` flag, but the component developer may override this behavior if a more complex algorithm is needed to determine the active/passive nature of the agent.

class pyuvm.s13_predefined_component_classes.uvm_driver(name, parent)

  Bases: `uvm_component`

  The base class for drivers that initiate requests for new transactions via a `uvm_seq_item_pull_port`. The ports are typically connected to the exports of an appropriate sequencer component.

  This driver operates in pull mode. Its ports are typically connected to the corresponding exports in a pull sequencer as follows:

      driver.seq_item_port.connect(sequencer.seq_item_export)
      driver.rsp_port.connect(sequencer.rsp_export)

  The `rsp_port` needs connecting only if the driver will use it to write responses to the analysis export in the sequencer.

class pyuvm.s13_predefined_component_classes.uvm_env(name, parent)

  Bases: `uvm_component`

  The base class for hierarchical containers of other components that together comprise a complete environment. The environment may initially consist of the entire testbench. Later, it can be reused as a sub-environment in even larger system-level environments.

class pyuvm.s13_predefined_component_classes.uvm_monitor(name, parent)

  Bases: `uvm_component`

  This class should be used as the base class for user-defined monitors.

  Deriving from `uvm_monitor` allows you to distinguish monitors from generic component types inheriting from `uvm_component`. Such monitors will automatically inherit features that may be added to `uvm_monitor` in the future.

class pyuvm.s13_predefined_component_classes.uvm_scoreboard(name, parent)

  Bases: `uvm_component`

  This class should be used as the base class for user-defined scoreboards.

  Deriving from `uvm_scoreboard` will allow you to distinguish scoreboards from other component types inheriting directly from `uvm_component`. Such scoreboards will automatically inherit and benefit from features that may be added to `uvm_scoreboard` in the future.

class pyuvm.s13_predefined_component_classes.uvm_subscriber(name, parent)

  Bases: `uvm_component`

  This class provides an analysis export for receiving transactions from a connected analysis export. Making such a connection “subscribes” this component to any transactions emitted by the connected analysis port.

  Subtypes of this class must define the write method to process the incoming transactions. This class is particularly useful when designing a coverage collector that attaches to a monitor.

  class uvm_AnalysisImp(name, parent, write_fn)

    Bases: `uvm_analysis_export`

    write(tt)

      Write a transaction to all the connected subscribers.

      Parameters:

        tt – The transaction to write

      Returns:

        None

  write(tt)

    Method that must be defined in each subclass. Access to this method by outside components should be done via the `analysis_export`.

class pyuvm.s13_predefined_component_classes.uvm_test(name, parent)

  Bases: `uvm_component`

  The base class for all tests

## pyuvm.s13_uvm_component module

class pyuvm.s13_uvm_component.ConfigDB(*args, **kwargs)

  Bases: `object`

  clear()

    Reset the ConfigDB. Used for testing.

  default_get = <object object>
  default_precedence = 1000
  exists(context, inst_name, field_name)

    Returns true if there is data in the database at this location

    Parameters:

      - context – None or uvm_component

      - inst_name – instance name string in context

      - field_name – key name for location

    Returns:

      True if exists

  get(context, inst_name, field_name, default=<object object>)

    The component path matches against the paths in the ConfigDB. The path cannot have wildcards, but can match against keys with wildcards. Return the value stored at key. If the key is missing, returns default or raises `UVMConfigItemNotFound`.

    Parameters:

      - context – The component making the call

      - inst_name – component full path with no wildcards

      - field_name – the field_name being retrieved

      - default – the value to return if there is no key, defaults to default_get

    Raises:

      UVMConfigItemNotFound – if the key is not found and the

    default is not set :return: value found at location

  legal_chars = {'.', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '_', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z'}

    A path-based singleton storage system

  set(context, inst_name, field_name, value)

    Stores an object in the db using the context and inst_name to create a retrieval path, and the key name.

    Parameters:

      - context – A handle to a component

      - inst_name – The instance name within the component

      - field_name – The key we’re setting

      - value – The object to be stored

    Returns:

      None

  trace(method, context, inst_name, field_name, value)

    Output the ConfigDB activity if tracing is on.

  wait_modified()
    Raises:

      UVMNotImplemented – This is not implemented in pyuvm

class pyuvm.s13_uvm_component.uvm_component(name, parent)

  Bases: `uvm_report_object`

  add_child(name, child)
  add_logging_handler_hier(handler)

    Add an additional handler all the way down the component hierarchy

    Parameters:

      handler – A logging.Handler object

    Returns:

      None

  build_phase()
  cdb_get(label, inst_path='')

    A convenience routine that retrieves an object from the config_db using this component’s `get_full_name()` path. Can find objects stored with wildcards

    Parameters:

      - inst_path – The path below this component

      - label – The label used to store the value

    Returns:

      The object at this path stored at the label

  cdb_set(label, value, inst_path='*')

    A convenience routing to store an object in the config_db using this component’s `get_full_name()` path.

    Parameters:

      - value – The object to store

      - label – The label to use to retrieve it

      - inst_path – A path with globs or if left blank the get_full_name() path

  check_phase()
  property children

    13.1.3.4 Implements the intention of this requirement without the approach taken in the UVM We use a generator instead.

  clear_children()

    Removes the direct children from this component.

  classmethod clear_components()
  clear_hierarchy()

    Removes self from the UVM hierarchy

  component_dict = {}
  connect_phase()
  classmethod create(name='', parent=None)
    Returns:

      new object from factory

  disable_logging_hier()

    Disable logging for this component and all the way down the hierarchy

  do_execute_op(op)

    Not implemented.

  drop_objection()

    Drop an objection, usually at the end of the `run_phase()`

  end_of_elaboration_phase()
  extract_phase()
  final_phase()
  get_child(name)

    13.1.3.4 :param self: :param name: child’s name :return: child `uvm_component` of that name

  get_children()

    13.1.3.3 :return: A dict containing children objects

  get_depth()

    13.1.3.8 Get the depth that I am from the top component. uvm_root is 0.

    Returns:

      The hierarchy depth from me to the bottom.

  get_full_name()
    Returns:

      This component’s name concatenated to parent name.

    13.1.3.2

  get_num_children()

    13.1.3.5 :param self: :return: The number of children in component

  get_parent()
    Returns:

      parent object

    13.1.3.1

  has_child(name)

    13.1.3.6 :param name: Name of child the object :return: True if exists, False otherwise

  property hierarchy

    We return a generator to find the children. This is more pythonic and saves memory for large hierarchies.

    Returns:

      A generator that returns the children.

  lookup(name)

    13.1.3.7 Return a component base on the path. If . then use full name from root otherwise relative

    Parameters:

      name – The search name

    Returns:

      either the component or None

  objection()
  property parent
  raise_objection()

    Raise an objection, usually at the start of the `run_phase()`

  remove_logging_handler_hier(handler)

    Remove a handler from all loggers below this component

    Parameters:

      handler – logging handler

    Returns:

      None

  remove_streaming_handler_hier()

    Remove this component’s streaming handler and all the way down the hierarchy

  report_phase()
  async run_phase()
  set_logging_level_hier(logging_level)

    Set the logging level for this component’s logger and all the way down the hierarchy

    Parameters:

      logging_level – typically a constant from logging module

    Returns:

      None

  start_of_simulation_phase()

class pyuvm.s13_uvm_component.uvm_root(*args, **kwargs)

  Bases: `uvm_component`

  F.7. We do not use `uvm_pkg` to hold `uvm_root`. Instead it is a class variable of uvm_component. This avoids circular reference issues regarding uvm_pkg.

  Plus, it’s cleaner.

  `uvm_root` is still a singleton that you access through its constructor instead of through a `get()` method.

  Much of the functionality in Annex F delivers functionality in SystemVerilog that is already built into Python. So we’re going to skip much of that Annex.

  classmethod clear_singletons(keep_set={})

    Clear the singletons in the system. This is used for testing

  async run_test(test_name, keep_singletons=False, keep_set={})
    Parameters:

      - test_name – The uvm test name or test class

      - keep_singletons – If True do not clear singletons (default False)

      - keep_set – Set of singleton classes to keep if keep_singletons is False. Pass a list of singletons to set()

    Returns:

      none

class pyuvm.s13_uvm_component.uvm_test(name, parent)

  Bases: `uvm_component`

  The base class for all tests

## pyuvm.s14_15_python_sequences module

class pyuvm.s14_15_python_sequences.ResponseQueue(maxsize: int = 0)

  Bases: `UVMQueue`

  The `ResponseQueue` is a queue that can cherry-pick an item using an id number, or simply return the next item in the queue.

  async get_response(txn_id=None)

    A coroutine that will either get a response item with the given transaction_id, or return the next item in the queue.

    Parameters:

      txn_id – (Optional) The transaction ID of the response you want

    to pluck from the queue. :return: The response item

  put_nowait(item)

    Extend the `cocotb.queue.Queue.put_nowait` method to set the `put_event` flag. This flag is used to signal that an item has been put in the queue so that get_response can be unblocked.

    Parameters:

      item – The item to put in the queue

    Raises:

      QueueFull – If the queue is full

class pyuvm.s14_15_python_sequences.uvm_seq_item_export(name, parent)

  Bases: `uvm_blocking_put_export`

  The sequence item port with a request queue and a response queue.

  async get_next_item()

    A couroutine that gets the next item out of the item queue and blocks if the queue is empty.

    Returns:

      item to process

  async get_response(transaction_id=None)

    A couroutine that will block if there is no transaction available

    If `transaction_id` is not `None`, block until a response with the transaction id becomes available.

    Parameters:

      transaction_id – The transaction ID of the response

    Returns:

      The response item

  item_done(rsp=None)

    Signal that the item has been completed. If `rsp` is not `None` put it into the response queue.

    Parameters:

      rsp – (optional) item to put in response queue if not None

  async put_req(item)

    put request into request queue. Block if the queue is full.

    Parameters:

      item – request item

    Returns:

      None

  put_response(item)

    Put response into response queue. Do not block.

    Parameters:

      item – response item

    Raises:

      QueueFull – If the queue is full

    Returns:

class pyuvm.s14_15_python_sequences.uvm_seq_item_port(name, parent)

  Bases: `uvm_port_base`

  connect(export)
    Parameters:

      export – The export that has the functions

    Raises:

      UVMTLMConnectionError if there is a connect error

    Returns:

      None

    Attach this port to the associated export.

  async get_next_item()

    A coroutine that get the next sequence item from the request queue and blocks if the queue is empty.

    Returns:

      The next sequence item

  async get_response(transaction_id=None)

    A coroutine that will ither get a response item with the given transaction_id, or get the first response item in the queue. Otherwise it will block until a response is ready.

    Parameters:

      transaction_id – The transaction ID of the response you want

    Returns:

      The response item

  item_done(rsp=None)

    Notify the driver that it can get the next sequence. If `rsp` is not `None`, put it in the response queue.

    Parameters:

      rsp – (optional) The response item

    Raises:

      UVMFatalError – If `rsp` is not a subclass of uvm_sequence_item

  async put_req(item)

    A coroutine that blocks until the request is put in the queue

    Parameters:

      item – The request item

  put_response(item)

    Put a response back in the queue. aka put_response

    Parameters:

      item – The response item

    Raises UVMFatalError:

      If the item is not a subclass of

    uvm_sequence_item

class pyuvm.s14_15_python_sequences.uvm_sequence(name='uvm_sequence')

  Bases: `uvm_object`

  The uvm_sequence creates a series of sequence items and feeds them to the sequencer using start_item() and finish_item(). It can also get back results with get_response() body() gets launched in a thread at start.

  async body()

    This function gets launched in a thread when you run start() You generally override it.

  async finish_item(item)
  async get_response(transaction_id=None)
  async post_body()

    This function gets launced AFTER the function body() is started following a start() call.

    This method should not be called directly by the user.

  async pre_body()

    This function gets launced BEFORE the function body() is started following a start() call.

    This method should not be called directly by the user.

  async start(seqr=None, call_pre_post=True)

    Launch this sequence on the sequencer. Seqr cannot be None.

    Parameters:

      - seqr – The sequencer to launch this sequence on.

      - call_pre_post – If set to true (default), then pre_body and

    post_body are called before and after the sequence body is called. :raise AssertionError: If seqr is None

  async start_item(item)

    Sends an item to the sequencer and waits to be notified when the item has been selected to be run.

    Parameters:

      item – The sequence item to send to the driver.

class pyuvm.s14_15_python_sequences.uvm_sequence_item(name)

  Bases: `uvm_transaction`

  The pyuvm uvm_sequence_item has events to implement start_item() and finish_item()

  set_context(item)

    Use this to link a new response transaction to the request transaction. rsp.set_context(req)

    Parameters:

      item – The request transaction

    Returns:

      None

class pyuvm.s14_15_python_sequences.uvm_sequencer(name, parent)

  Bases: `uvm_component`

  The uvm_sequencer arbitrates between multiple sequences that want to send items to driver (connected to seq_export) It exposes put_req, get_next_item, get_response from the export. The sequence will use these to coordinate items with the sequencer.

  async finish_item(item)
  async get_next_item()
  async get_response(txn_id=None)
  async put_req(req)
  async run_phase()
  async start_item(item)

## pyuvm.s17_uvm_reg_enumerations module

class pyuvm.s17_uvm_reg_enumerations.uvm_access_e(*values)

  Bases: `Enum`

  UVM_READ = 0
  UVM_WRITE = 1

class pyuvm.s17_uvm_reg_enumerations.uvm_check_e(*values)

  Bases: `Enum`

  UVM_CHECK = 1
  UVM_NO_CHECK = 0

class pyuvm.s17_uvm_reg_enumerations.uvm_coverage_model_e(*values)

  Bases: `Enum`

  UVM_CVR_ADDR_MAP = 2
  UVM_CVR_ALL = 4
  UVM_CVR_FIELD_VALS = 3
  UVM_CVR_REG_BITS = 1
  UVM_NO_COVERAGE = 0

class pyuvm.s17_uvm_reg_enumerations.uvm_door_e(*values)

  Bases: `Enum`

  UVM_BACKDOOR = 1
  UVM_DEFAULT_DOOR = 3
  UVM_FRONTDOOR = 0
  UVM_PREDICT = 2

class pyuvm.s17_uvm_reg_enumerations.uvm_elem_kind_e(*values)

  Bases: `Enum`

  UVM_FIELD = 1
  UVM_MEM = 2
  UVM_REG = 0

class pyuvm.s17_uvm_reg_enumerations.uvm_endianness_e(*values)

  Bases: `Enum`

  UVM_BIG_ENDIAN = 2
  UVM_BIG_FIFO = 4
  UVM_LITTLE_ENDIAN = 1
  UVM_LITTLE_FIFO = 3
  UVM_NO_ENDIAN = 0

class pyuvm.s17_uvm_reg_enumerations.uvm_hdl_path_concat(name='unnamed')

  Bases: `uvm_object`

  add_slice(slice_i: uvm_hdl_path_slice) → None
  get_slices() → list
  set_slices(slices: list)

class pyuvm.s17_uvm_reg_enumerations.uvm_hdl_path_slice(path: str, offset: int, size: int)

  Bases: `object`

  offset: int
  path: str
  size: int

class pyuvm.s17_uvm_reg_enumerations.uvm_hier_e(*values)

  Bases: `Enum`

  UVM_HIER = 1
  UVM_NO_HIER = 0

class pyuvm.s17_uvm_reg_enumerations.uvm_predict_e(*values)

  Bases: `Enum`

  UVM_PREDICT_DIRECT = 0
  UVM_PREDICT_READ = 1
  UVM_PREDICT_WRITE = 2

class pyuvm.s17_uvm_reg_enumerations.uvm_reg_mem_tests_e(*values)

  Bases: `Enum`

  UVM_DO_ALL_REG_MEM_TESTS = 6
  UVM_DO_MEM_ACCESS = 3
  UVM_DO_MEM_WALK = 5
  UVM_DO_REG_ACCESS = 2
  UVM_DO_REG_BIT_BASH = 1
  UVM_DO_REG_HW_RESET = 0
  UVM_DO_SHARED_ACCESS = 4

class pyuvm.s17_uvm_reg_enumerations.uvm_status_e(*values)

  Bases: `Enum`

  UVM_HAS_X = 2
  UVM_IS_OK = 0
  UVM_NOT_OK = 1

## pyuvm.s18_uvm_reg_block module

class pyuvm.s18_uvm_reg_block.uvm_reg_block(name='uvm_reg_block')

  Bases: `uvm_object`

  add_block(in_blk)
  add_coverage()
  add_hdl_path(path: str, kind='RTL')
  blk_add_map(map_i: uvm_reg_map)
  blk_create_map(name: str, base_addr: int)
  blk_get_def_map()
  blk_is_child_mapped(in_blk) → bool
  blk_is_map_mapped(map_i: uvm_reg_map)
  blk_is_reg_mapped(reg: uvm_reg) → bool
  blk_set_map_mapping(map_i: uvm_reg_map)
  blk_set_reg_mapping(reg: uvm_reg)
  clear_hdl_path(kind='RTL')
  configure_blk(parent, hdl_path)
  gen_message(txt='') → str
  get_all_child_blk() → list
  get_blk_full_name() → str
  get_coverage()
  get_field_by_name(namei: str) → uvm_reg_field
  get_fields(hier=uvm_hier_e.UVM_HIER) → list
  get_full_hdl_path(paths: list, kind='', separator='.')
  get_hdl_path(paths: list, kind='')
  get_map_by_name(namei: str)
  get_reg_by_name(namei: str) → uvm_reg
  get_registers(hier=uvm_hier_e.UVM_HIER) → list
  has_coverage()
  has_hdl_path(kind: str) → bool
  is_locked() → bool
  reset_blk()
  sample_values()
  set_coverage(is_on: bool)
  set_default_map(mapi: uvm_reg_map)
  set_lock()

## pyuvm.s19_uvm_reg_field module

class pyuvm.s19_uvm_reg_field.uvm_reg_field(name='uvm_reg_field')

  Bases: `uvm_object`

  configure(parent: uvm_reg, size: int, lsb_pos: int, access: str, is_volatile: bool, reset: int)
  do_predict(rw: uvm_reg_item, kind: uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, be: int = -1)
  field_lock()
  field_set(value: int)
  field_unlock()
  get()
  get_access() → str
  get_compare()
  get_full_name()
    Returns:

      The full path and name of the object

    The full name for a uvm_object is simply the name

  get_lsb_pos() → int
  get_msb_pos() → int
  get_n_bits() → int
  get_parent()
  get_reset() → int
  get_response()
  get_value()
  is_known_access() → bool
  is_volatile() → bool
  predict(value: int, be: int = -1, kind: uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, path: uvm_door_e = uvm_door_e.UVM_FRONTDOOR, map: uvm_reg_map = None, fname: str = '', lineno: int = 0) → bool
  predict_read() → Tuple[bool, int]
  predict_response(path: path_t, direction: access_e)
  predict_write(cur_val, wr_val) → int
  reset()
  set_access(access_value)
  set_compare(check_type: check_t)
  set_response(f_response: uvm_resp_t)
  set_throw_error_on_read(teor=False)
  set_throw_error_on_write(teow=False)

## pyuvm.s20_uvm_reg module

class pyuvm.s20_uvm_reg.uvm_reg(name='uvm_reg', reg_width=32)

  Bases: `uvm_object`

  add_map(map_i: uvm_reg_map)
  build()

    This function needs to be implemented into the child class create each fields and invoke the configure from each field

  check_err_list()
  configure(parent, address: str, hdl_path: str, throw_error_on_read: bool = False, throw_error_on_write: bool = False)
  do_predict(rw: uvm_reg_item, kind: uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, be: int = -1)
  gen_message(mss: str) → str
  get_access_policy() → str
  get_address()
  get_desired()
  get_fields()
  get_mirrored_value()
  get_parent()
  get_reg_size() → int
  predict(value: int, be: int = -1, kind: uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, path: uvm_door_e = uvm_door_e.UVM_FRONTDOOR, map: uvm_reg_map = None, fname: str = '', lineno: int = 0) → bool
  async read(map: uvm_reg_map, path: path_t, check: check_t)
  reset()
  sample_values()
  set_access_policy(policy: str = 'RW')
  set_coverage(is_on: bool)
  set_desired(value)
  async write(value: int, map: uvm_reg_map, path: path_t, check: check_t) → uvm_resp_t

## pyuvm.s21_uvm_reg_map module

class pyuvm.s21_uvm_reg_map.uvm_reg_map(name='uvm_reg_map')

  Bases: `uvm_object`

  add_parent_map(parent_map)
  add_reg(reg, offset: str = '0x0', rights: str = 'RW')
  add_submap(submap)
  check_process_integrity(adapter=None, reg_item=None)
  configure(parent, base_addr)
  gen_message(txt='') → str
  get_adapter()
  get_endian()
  get_full_name()
    Returns:

      The full path and name of the object

    The full name for a uvm_object is simply the name

  get_n_bytes()
  get_offset()
  get_parent()
  get_parent_map()
  get_predictor()
  get_reg_by_offset(offset)
  get_registers(as_dict=False)
  get_root_map()
  get_sequencer()
  get_submaps(as_dict=False)
  async process_read_operation(reg_address, path: path_t, check: check_t)
  async process_write_operation(reg_address, data_to_be_written, path: path_t, check: check_t)
  reset(reset_type: str)
  set_adapter(adapter)
  set_predictor(predictor)
  set_sequencer(sequencer)
  verify_map_config()

## pyuvm.s22_uvm_mem module

class pyuvm.s22_uvm_mem.uvm_mem(name='uvm_mem')

  Bases: `uvm_object`

## pyuvm.s23_uvm_reg_item module

class pyuvm.s23_uvm_reg_item.uvm_reg_item(name='item')

  Bases: `uvm_sequence_item`

  do_copy(rhs)
    Parameters:

      rhs – The object to copy from

    Returns:

      None

    By default we copy the name. Override this function to copy the rest of the object members.

  get_bd_kind()
  get_door()
  get_element()
  get_element_kind()
  get_extension()
  get_fname() → str
  get_kind()
  get_line()
  get_offset()
  get_parent_sequence()
  get_status()
  get_value(idx=0)
  get_value_array()
  get_value_size()
  set_bd_kind(val)
  set_door(door)
  set_element(el)
  set_element_kind(_kind)
  set_extension(ext)
  set_fname(fname: str)
  set_kind(_kind)
  set_line(line: int)
  set_map(map_input)
  set_offset(offset)
  set_parent_sequence(seq: None)
  set_status(status)
  set_value(value, idx=0)
  set_value_array(v)
  set_value_size(sz)

## pyuvm.s24_uvm_reg_includes module

Collection of defines to be sued

class pyuvm.s24_uvm_reg_includes.access_e(*values)

  Bases: `Enum`

  access_e type of access allowed PYUVM_READ = 0 PYUVM_WRITE = 1

  UVM_READ = 0
  UVM_WRITE = 1

class pyuvm.s24_uvm_reg_includes.check_t(*values)

  Bases: `Enum`

  Check TYPE

  CHECK = 1
  NO_CHECK = 2

class pyuvm.s24_uvm_reg_includes.elem_kind_e(new_class_name, /, names, *, module=None, qualname=None, type=None, start=1, boundary=None)

  Bases: `Enum`

pyuvm.s24_uvm_reg_includes.error_out(header, message)

  Used to error out based on header and message

class pyuvm.s24_uvm_reg_includes.path_t(*values)

  Bases: `Enum`

  Access TYPE

  BACKDOOR = 2
  FRONTDOOR = 1
  USER_FRONTDOOR = 3

class pyuvm.s24_uvm_reg_includes.predict_t(*values)

  Bases: `Enum`

  predict_t main prediction to be used PREDICT_WRITE = 1 PREDICT_READ = 2 PREDICT_DIRECT = 3

  PREDICT_DIRECT = 3
  PREDICT_READ = 2
  PREDICT_WRITE = 1

pyuvm.s24_uvm_reg_includes.rand_enable(use_pyvsc: bool)

  New Decorator class with randomization option If the randomization is switched off then the decorator will no more use py_vsc but it just disables it allowing user to use local methods if needed

class pyuvm.s24_uvm_reg_includes.status_t(*values)

  Bases: `Enum`

  Status TYPE

  IS_NOT_OK = 2
  IS_OK = 1

pyuvm.s24_uvm_reg_includes.uvm_error(header='', message='')

  Used to error out based on header and message

pyuvm.s24_uvm_reg_includes.uvm_fatal(header='', message='')

  Used to fatal out based on header and message

pyuvm.s24_uvm_reg_includes.uvm_not_implemeneted(header='', message='')

  Used to fatal out based on header and message

class pyuvm.s24_uvm_reg_includes.uvm_reg_bus_op

  Bases: `object`

  Standard class for register bus operation to be used into the Prediction or Adapter

  addr: int
  byte_en: bool
  data: int
  kind: access_e
  n_bits: int
  status: uvm_resp_t

class pyuvm.s24_uvm_reg_includes.uvm_reg_error_decoder(*values)

  Bases: `Enum`

  List of uvm_reg errors to be collected FIELD_CANNOT_BE_NONE = 1 FIELD_ALREADY_ADDED = 2 FIELD_DOESNT_FIT_INTO_REG = 3 FIELD_OVERLAPPING_ERROR = 4 REG_SIZE_CANNOT_BE_ZERO = 5

  FIELD_ALREADY_ADDED = 2
  FIELD_CANNOT_BE_NONE = 1
  FIELD_DOESNT_FIT_INTO_REG = 3
  FIELD_OVERLAPPING_ERROR = 4
  REG_SIZE_CANNOT_BE_ZERO = 5

class pyuvm.s24_uvm_reg_includes.uvm_reg_field_error_decoder(*values)

  Bases: `Enum`

  List of uvm_reg errors to be collected CONFIGURE_MUST_BE_CALLED_BEFORE = 1 ACCESS_TYPE_NEEDS_TO_BE_A_STRING = 2 WRONG_ACCESS_FOR_PREDICT_READ = 3 WRONG_COMBINATION_PREDICTION_DIRECTION = 4 ACCESS_VALUE_OUT_OF_LIST = 5

  ACCESS_TYPE_NEEDS_TO_BE_A_STRING = 2
  ACCESS_VALUE_OUT_OF_LIST = 5
  CONFIGURE_MUST_BE_CALLED_BEFORE = 1
  WRONG_ACCESS_FOR_PREDICT_READ = 3
  WRONG_COMBINATION_PREDICTION_DIRECTION = 4

class pyuvm.s24_uvm_reg_includes.uvm_resp_t(*values)

  Bases: `Enum`

  uvm_resp_t is the main response based on the access issued PASS_RESP = 0 ERROR_RESP = 1

  ERROR_RESP = 1
  PASS_RESP = 0

## pyuvm.s25_uvm_adapter module

class pyuvm.s25_uvm_adapter.uvm_reg_adapter(name='uvm_reg_adapter')

  Bases: `uvm_object`

  bus2reg(bus_item: uvm_sequence_item, rw: uvm_reg_bus_op)
  get_byte_en()
  get_item()
  get_parent_sequence()
  get_provide_reponse()
  reg2bus(rw: uvm_reg_bus_op) → uvm_sequence_item
  set_item(item: uvm_reg_item)
  set_parent_sequence(sequence: uvm_sequence)

## pyuvm.s26_uvm_predictor module

class pyuvm.s26_uvm_predictor.uvm_reg_predictor(name='uvm_reg_predictor')

  Bases: `uvm_object`

## pyuvm.s27_uvm_reg_pkg module

## pyuvm.utility_classes module

class pyuvm.utility_classes.FactoryData(*args, **kwargs)

  Bases: `object`

  clear_classes()
  clear_overrides()
  find_override(requested_type, inst_path=None, overridden_list=None)
    Parameters:

      - requested_type – The type we’re overriding

      - inst_path – The inst_path we’re using to override if any

      - overridden_list – A list of previously found overrides

    Returns:

      overriding_type

    Override searches are recursively applied, with instance overrides taking precedence over type overrides. If foo overrides bar, and xyz overrides foo, then a request for bar returns xyx.

class pyuvm.utility_classes.FactoryMeta(name, bases, cls_dict)

  Bases: `type`

  This is the metaclass that causes all uvm_void classes to register themselves

class pyuvm.utility_classes.ObjectionHandler(*args, **kwargs)

  Bases: `object`

  This singleton accepts objections and then allows them to be removed. It returns True to run_phase_complete() when there are no objections left.

  clear()
  drop_objection(dropper)
  raise_objection(raiser)
  async run_phase_complete()

class pyuvm.utility_classes.Override

  Bases: `object`

  This class stores an override and an optional path. It is intended to be stored in a dict with the original class as the key.

  add(override, path=None)
  find_inst_override(path)

class pyuvm.utility_classes.Singleton

  Bases: `type`

  classmethod clear_singletons(keep)

class pyuvm.utility_classes.UVMQueue(maxsize: int = 0)

  Bases: `Queue`

  The UVMQueue provides a peek function as well as the ability to break out of a blocking operation if the time_to_die predicate is true. The time to die is set to the dropping of all run_phase objections by default.

  async peek()

    Remove and return an item from the queue. If the queue is empty, wait until an item is available.

  peek_nowait()

    Remove and return an item from the queue. Return an item if one is immediately available, else raise `asyncio.QueueEmpty`.

class pyuvm.utility_classes.UVM_ROOT_Singleton(name, bases, cls_dict)

  Bases: `FactoryMeta`

  classmethod clear_singletons()
  singleton = None

pyuvm.utility_classes.count_bits(nn)

  Count the number of bits in a number

  Parameters:

    nn – The number to count the bits in

  Returns:

    The number of bits

class pyuvm.utility_classes.uvm_void

  Bases: `object`

  5.2 SystemVerilog Python uses this class to allow all uvm objects to be stored in a uvm_void variable through polymorphism.

  In pyuvm, we’re using uvm_void() as a metaclass so that all UVM classes can be stored in a factory.

## Module contents