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v2.2.0 (RP2040)
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hardware_clocks

Clock Management API. More...

## Macros

#define | GPIO_TO_GPOUT_CLOCK_HANDLE
| Returns the GPOUT clock number associated with a particular GPIO if there is one, or default_clk_handle otherwise.

## Typedefs

typedef enum clock_num_rp2040 | clock_num_t
| Clock numbers on RP2040 (used as typedef clock_num_t).
typedef enum clock_dest_num_rp2040 | clock_dest_num_t
| Clock destination numbers on RP2040 (used as typedef clock_dest_num_t).
typedef void(* | resus_callback_t) (void)
| Resus callback function type.

## Enumerations

enum | clock_num_rp2040 { clk_gpout0 = 0 , clk_gpout1 = 1 , clk_gpout2 = 2 , clk_gpout3 = 3 , clk_ref = 4 , clk_sys = 5 , clk_peri = 6 , clk_usb = 7 , clk_adc = 8 , clk_rtc = 9 , CLK_COUNT }
| Clock numbers on RP2040 (used as typedef clock_num_t). More...

enum

clock_dest_num_rp2040 {
CLK_DEST_SYS_CLOCKS = 0 , CLK_DEST_ADC_ADC = 1 , CLK_DEST_SYS_ADC = 2 , CLK_DEST_SYS_BUSCTRL = 3 ,
CLK_DEST_SYS_BUSFABRIC = 4 , CLK_DEST_SYS_DMA = 5 , CLK_DEST_SYS_I2C0 = 6 , CLK_DEST_SYS_I2C1 = 7 ,
CLK_DEST_SYS_IO = 8 , CLK_DEST_SYS_JTAG = 9 , CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10 , CLK_DEST_SYS_PADS = 11 ,
CLK_DEST_SYS_PIO0 = 12 , CLK_DEST_SYS_PIO1 = 13 , CLK_DEST_SYS_PLL_SYS = 14 , CLK_DEST_SYS_PLL_USB = 15 ,
CLK_DEST_SYS_PSM = 16 , CLK_DEST_SYS_PWM = 17 , CLK_DEST_SYS_RESETS = 18 , CLK_DEST_SYS_ROM = 19 ,
CLK_DEST_SYS_ROSC = 20 , CLK_DEST_RTC_RTC = 21 , CLK_DEST_SYS_RTC = 22 , CLK_DEST_SYS_SIO = 23 ,
CLK_DEST_PERI_SPI0 = 24 , CLK_DEST_SYS_SPI0 = 25 , CLK_DEST_PERI_SPI1 = 26 , CLK_DEST_SYS_SPI1 = 27 ,
CLK_DEST_SYS_SRAM0 = 28 , CLK_DEST_SYS_SRAM1 = 29 , CLK_DEST_SYS_SRAM2 = 30 , CLK_DEST_SYS_SRAM3 = 31 ,
CLK_DEST_SYS_SRAM4 = 32 , CLK_DEST_SYS_SRAM5 = 33 , CLK_DEST_SYS_SYSCFG = 34 , CLK_DEST_SYS_SYSINFO = 35 ,
CLK_DEST_SYS_TBMAN = 36 , CLK_DEST_SYS_TIMER = 37 , CLK_DEST_PERI_UART0 = 38 , CLK_DEST_SYS_UART0 = 39 ,
CLK_DEST_PERI_UART1 = 40 , CLK_DEST_SYS_UART1 = 41 , CLK_DEST_SYS_USBCTRL = 42 , CLK_DEST_USB_USBCTRL = 43 ,
CLK_DEST_SYS_WATCHDOG = 44 , CLK_DEST_SYS_XIP = 45 , CLK_DEST_SYS_XOSC = 46 , NUM_CLOCK_DESTINATIONS
}

| Clock destination numbers on RP2040 (used as typedef clock_dest_num_t). More...

## Functions

bool | clock_configure (clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq)
| Configure the specified clock with automatic clock divisor setup.
void | clock_configure_undivided (clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq)
| Configure the specified clock to use the undivided input source.
void | clock_configure_int_divider (clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t int_divider)
| Configure the specified clock to use the undivided input source.
void | clock_stop (clock_handle_t clock)
| Stop the specified clock.
uint32_t | clock_get_hz (clock_handle_t clock)
| Get the current frequency of the specified clock.
uint32_t | frequency_count_khz (uint src)
| Measure a clocks frequency using the Frequency counter.
void | clock_set_reported_hz (clock_handle_t clock, uint hz)
| Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock.
void | clocks_enable_resus (resus_callback_t resus_callback)
| Enable the resus function. Restarts clk_sys if it is accidentally stopped.
void | clock_gpio_init_int_frac16 (uint gpio, uint src, uint32_t div_int, uint16_t div_frac16)
| Output an optionally divided clock to the specified gpio pin.
static void | clock_gpio_init_int_frac8 (uint gpio, uint src, uint32_t div_int, uint8_t div_frac8)
| Output an optionally divided clock to the specified gpio pin.
static void | clock_gpio_init (uint gpio, uint src, float div)
| Output an optionally divided clock to the specified gpio pin.
bool | clock_configure_gpin (clock_handle_t clock, uint gpio, uint32_t src_freq, uint32_t freq)
| Configure a clock to come from a gpio input.
void | set_sys_clock_48mhz (void)
| Initialise the system clock to 48MHz.
void | set_sys_clock_pll (uint32_t vco_freq, uint post_div1, uint post_div2)
| Initialise the system clock.
bool | check_sys_clock_hz (uint32_t freq_hz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out)
| Check if a given system clock frequency is valid/attainable.
bool | check_sys_clock_khz (uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out)
| Check if a given system clock frequency is valid/attainable.
static bool | set_sys_clock_hz (uint32_t freq_hz, bool required)
| Attempt to set a system clock frequency in hz.
static bool | set_sys_clock_khz (uint32_t freq_khz, bool required)
| Attempt to set a system clock frequency in khz.
static clock_handle_t | gpio_to_gpout_clock_handle (uint gpio, clock_handle_t default_clk_handle)
| return the associated GPOUT clock for a given GPIO if any

## Detailed Description

Clock Management API.

This API provides a high level interface to the clock functions.

The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock sources allowing the user to trade off performance against cost, board area and power consumption. From these sources it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies

Please refer to the appropriate datasheet for more details on the RP-series clocks.

The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary clock source, then you will need to use one of the entries from the subsequent tables.

- On RP2040 the clock sources are:

Main Clock Sources

Source | Reference Clock | System Clock
--- | --- | ---
ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH |
Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX
XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC |
Reference |  | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF

Auxiliary Clock Sources

The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3.

Aux Source | clk_gpout[x] | clk_ref | clk_sys
--- | --- | --- | ---
System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS |  | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC |  | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC |  | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS |  |
USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB |  |
ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC |  |
RTC Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_RTC |  |
Ref clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF |  |

Aux Source | clk_peri | clk_usb | clk_adc
--- | --- | --- | ---
System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS |  |

Aux Source | clk_rtc
--- | ---
System PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
GPIO in 0 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
GPIO in 1 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
USB PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
ROSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
XOSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC

# Example

## Macro Definition Documentation

## GPIO_TO_GPOUT_CLOCK_HANDLE

#define GPIO_TO_GPOUT_CLOCK_HANDLE

Returns the GPOUT clock number associated with a particular GPIO if there is one, or default_clk_handle otherwise.

Note this macro is intended to resolve at compile time, and does no parameter checking

## Typedef Documentation

## resus_callback_t

typedef void(* resus_callback_t) (void)

Resus callback function type.

User provided callback for a resus event (when clk_sys is stopped by the programmer and is restarted for them).

## Enumeration Type Documentation

## clock_dest_num_rp2040

enum clock_dest_num_rp2040

Clock destination numbers on RP2040 (used as typedef clock_dest_num_t).

Enumerator
CLK_DEST_SYS_CLOCKS | Select SYS_CLOCKS as clock destination.
CLK_DEST_ADC_ADC | Select ADC_ADC as clock destination.
CLK_DEST_SYS_ADC | Select SYS_ADC as clock destination.
CLK_DEST_SYS_BUSCTRL | Select SYS_BUSCTRL as clock destination.
CLK_DEST_SYS_BUSFABRIC | Select SYS_BUSFABRIC as clock destination.
CLK_DEST_SYS_DMA | Select SYS_DMA as clock destination.
CLK_DEST_SYS_I2C0 | Select SYS_I2C0 as clock destination.
CLK_DEST_SYS_I2C1 | Select SYS_I2C1 as clock destination.
CLK_DEST_SYS_IO | Select SYS_IO as clock destination.
CLK_DEST_SYS_JTAG | Select SYS_JTAG as clock destination.
CLK_DEST_SYS_VREG_AND_CHIP_RESET | Select SYS_VREG_AND_CHIP_RESET as clock destination.
CLK_DEST_SYS_PADS | Select SYS_PADS as clock destination.
CLK_DEST_SYS_PIO0 | Select SYS_PIO0 as clock destination.
CLK_DEST_SYS_PIO1 | Select SYS_PIO1 as clock destination.
CLK_DEST_SYS_PLL_SYS | Select SYS_PLL_SYS as clock destination.
CLK_DEST_SYS_PLL_USB | Select SYS_PLL_USB as clock destination.
CLK_DEST_SYS_PSM | Select SYS_PSM as clock destination.
CLK_DEST_SYS_PWM | Select SYS_PWM as clock destination.
CLK_DEST_SYS_RESETS | Select SYS_RESETS as clock destination.
CLK_DEST_SYS_ROM | Select SYS_ROM as clock destination.
CLK_DEST_SYS_ROSC | Select SYS_ROSC as clock destination.
CLK_DEST_RTC_RTC | Select RTC_RTC as clock destination.
CLK_DEST_SYS_RTC | Select SYS_RTC as clock destination.
CLK_DEST_SYS_SIO | Select SYS_SIO as clock destination.
CLK_DEST_PERI_SPI0 | Select PERI_SPI0 as clock destination.
CLK_DEST_SYS_SPI0 | Select SYS_SPI0 as clock destination.
CLK_DEST_PERI_SPI1 | Select PERI_SPI1 as clock destination.
CLK_DEST_SYS_SPI1 | Select SYS_SPI1 as clock destination.
CLK_DEST_SYS_SRAM0 | Select SYS_SRAM0 as clock destination.
CLK_DEST_SYS_SRAM1 | Select SYS_SRAM1 as clock destination.
CLK_DEST_SYS_SRAM2 | Select SYS_SRAM2 as clock destination.
CLK_DEST_SYS_SRAM3 | Select SYS_SRAM3 as clock destination.
CLK_DEST_SYS_SRAM4 | Select SYS_SRAM4 as clock destination.
CLK_DEST_SYS_SRAM5 | Select SYS_SRAM5 as clock destination.
CLK_DEST_SYS_SYSCFG | Select SYS_SYSCFG as clock destination.
CLK_DEST_SYS_SYSINFO | Select SYS_SYSINFO as clock destination.
CLK_DEST_SYS_TBMAN | Select SYS_TBMAN as clock destination.
CLK_DEST_SYS_TIMER | Select SYS_TIMER as clock destination.
CLK_DEST_PERI_UART0 | Select PERI_UART0 as clock destination.
CLK_DEST_SYS_UART0 | Select SYS_UART0 as clock destination.
CLK_DEST_PERI_UART1 | Select PERI_UART1 as clock destination.
CLK_DEST_SYS_UART1 | Select SYS_UART1 as clock destination.
CLK_DEST_SYS_USBCTRL | Select SYS_USBCTRL as clock destination.
CLK_DEST_USB_USBCTRL | Select USB_USBCTRL as clock destination.
CLK_DEST_SYS_WATCHDOG | Select SYS_WATCHDOG as clock destination.
CLK_DEST_SYS_XIP | Select SYS_XIP as clock destination.
CLK_DEST_SYS_XOSC | Select SYS_XOSC as clock destination.

## clock_num_rp2040

enum clock_num_rp2040

Clock numbers on RP2040 (used as typedef clock_num_t).

Enumerator
clk_gpout0 | Select CLK_GPOUT0 as clock source.
clk_gpout1 | Select CLK_GPOUT1 as clock source.
clk_gpout2 | Select CLK_GPOUT2 as clock source.
clk_gpout3 | Select CLK_GPOUT3 as clock source.
clk_ref | Select CLK_REF as clock source.
clk_sys | Select CLK_SYS as clock source.
clk_peri | Select CLK_PERI as clock source.
clk_usb | Select CLK_USB as clock source.
clk_adc | Select CLK_ADC as clock source.
clk_rtc | Select CLK_RTC as clock source.

## Function Documentation

## check_sys_clock_hz()

bool check_sys_clock_hz | ( | uint32_t | freq_hz,
|  | uint * | vco_freq_out,
|  | uint * | post_div1_out,
|  | uint * | post_div2_out )

Check if a given system clock frequency is valid/attainable.

Parameters

  freq_hz | Requested frequency
  vco_freq_out | On success, the voltage controlled oscillator frequency to be used by the SYS PLL
  post_div1_out | On success, The first post divider for the SYS PLL
  post_div2_out | On success, The second post divider for the SYS PLL.

Returns
  true if the frequency is possible and the output parameters have been written.

## check_sys_clock_khz()

bool check_sys_clock_khz | ( | uint32_t | freq_khz,
|  | uint * | vco_freq_out,
|  | uint * | post_div1_out,
|  | uint * | post_div2_out )

Check if a given system clock frequency is valid/attainable.

Parameters

  freq_khz | Requested frequency
  vco_freq_out | On success, the voltage controlled oscillator frequency to be used by the SYS PLL
  post_div1_out | On success, The first post divider for the SYS PLL
  post_div2_out | On success, The second post divider for the SYS PLL.

Returns
  true if the frequency is possible and the output parameters have been written.

## clock_configure()

bool clock_configure | ( | clock_handle_t | clock,
|  | uint32_t | src,
|  | uint32_t | auxsrc,
|  | uint32_t | src_freq,
|  | uint32_t | freq )

Configure the specified clock with automatic clock divisor setup.

This method allows both the src_frequency of the input clock source AND the desired frequency to be specified, and will set the clock divider to achieve the exact or higher frequency achievable, with the maximum being the src_freq.

Note: The RP2040 clock hardware only supports divisors of exactly 1.0 or 2.0->16777216.0 in steps of 1/256

See the tables in the description for details on the possible values for clock sources.

Parameters

  clock | The clock to configure
  src | The main clock source, can be 0.
  auxsrc | The auxiliary clock source, which depends on which clock is being set. Can be 0
  src_freq | Frequency of the input clock source
  freq | Requested frequency

Returns
  true if the clock is updated, false if freq > src_freq

## clock_configure_gpin()

bool clock_configure_gpin | ( | clock_handle_t | clock,
|  | uint | gpio,
|  | uint32_t | src_freq,
|  | uint32_t | freq )

Configure a clock to come from a gpio input.

Parameters

  clock | The clock to configure
  gpio | The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22.
  src_freq | Frequency of the input clock source
  freq | Requested frequency

## clock_configure_int_divider()

void clock_configure_int_divider | ( | clock_handle_t | clock,
|  | uint32_t | src,
|  | uint32_t | auxsrc,
|  | uint32_t | src_freq,
|  | uint32_t | int_divider )

Configure the specified clock to use the undivided input source.

See the tables in the description for details on the possible values for clock sources.

Parameters

  clock | The clock to configure
  src | The main clock source, can be 0.
  auxsrc | The auxiliary clock source, which depends on which clock is being set. Can be 0
  src_freq | Frequency of the input clock source
  int_divider | an integer divider

## clock_configure_undivided()

void clock_configure_undivided | ( | clock_handle_t | clock,
|  | uint32_t | src,
|  | uint32_t | auxsrc,
|  | uint32_t | src_freq )

Configure the specified clock to use the undivided input source.

See the tables in the description for details on the possible values for clock sources.

Parameters

  clock | The clock to configure
  src | The main clock source, can be 0.
  auxsrc | The auxiliary clock source, which depends on which clock is being set. Can be 0
  src_freq | Frequency of the input clock source

## clock_get_hz()

uint32_t clock_get_hz | ( | clock_handle_t | clock | ) |

Get the current frequency of the specified clock.

Parameters

  clock | Clock

Returns
  Clock frequency in Hz

## clock_gpio_init()

void clock_gpio_init | ( | uint | gpio,
|  | uint | src,
|  | float | div )

inline static

Output an optionally divided clock to the specified gpio pin.

On RP2040 valid GPIOs are 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.

Parameters

  gpio | The GPIO pin to output the clock to.
  src | The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
  div | The float amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock.

## clock_gpio_init_int_frac16()

void clock_gpio_init_int_frac16 | ( | uint | gpio,
|  | uint | src,
|  | uint32_t | div_int,
|  | uint16_t | div_frac16 )

Output an optionally divided clock to the specified gpio pin.

On RP2040 valid GPIOs are 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.

Parameters

  gpio | The GPIO pin to output the clock to.
  src | The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
  div_int | The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040 and 1..2^16-1 on RP2350
  div_frac16 | The fractional part of the value to divide the source clock by. This is in range of 0..65535 (/65536).

## clock_gpio_init_int_frac8()

void clock_gpio_init_int_frac8 | ( | uint | gpio,
|  | uint | src,
|  | uint32_t | div_int,
|  | uint8_t | div_frac8 )

inline static

Output an optionally divided clock to the specified gpio pin.

- On RP2040 valid GPIOs are 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.

Parameters

  gpio | The GPIO pin to output the clock to.
  src | The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
  div_int | The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040 and 1..2^16-1 on RP2350
  div_frac8 | The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).

## clock_set_reported_hz()

void clock_set_reported_hz | ( | clock_handle_t | clock,
|  | uint | hz )

Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock.

See also
  clock_get_hz()

## clock_stop()

void clock_stop | ( | clock_handle_t | clock | ) |

Stop the specified clock.

Parameters

  clock | The clock to stop

## clocks_enable_resus()

void clocks_enable_resus | ( | resus_callback_t | resus_callback | ) |

Enable the resus function. Restarts clk_sys if it is accidentally stopped.

The resuscitate function will restart the system clock if it falls below a certain speed (or stops). This could happen if the clock source the system clock is running from stops. For example if a PLL is stopped.

Parameters

  resus_callback | a function pointer provided by the user to call if a resus event happens.

## frequency_count_khz()

uint32_t frequency_count_khz | ( | uint | src | ) |

Measure a clocks frequency using the Frequency counter.

Uses the inbuilt frequency counter to measure the specified clocks frequency. Currently, this function is accurate to +-1KHz. See the datasheet for more details.

## gpio_to_gpout_clock_handle()

clock_handle_t gpio_to_gpout_clock_handle | ( | uint | gpio,
|  | clock_handle_t | default_clk_handle )

inline static

return the associated GPOUT clock for a given GPIO if any

Returns
  the GPOUT clock number associated with a particular GPIO or default_clk_handle otherwise

## set_sys_clock_48mhz()

void set_sys_clock_48mhz | ( | void |  | ) |

Initialise the system clock to 48MHz.

Set the system clock to 48MHz, and set the peripheral clock to match.

## set_sys_clock_hz()

bool set_sys_clock_hz | ( | uint32_t | freq_hz,
|  | bool | required )

inline static

Attempt to set a system clock frequency in hz.

Note that not all clock frequencies are possible; it is preferred that you use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters for use with set_sys_clock_pll

Parameters

  freq_hz | Requested frequency
  required | if true then this function will assert if the frequency is not attainable.

Returns
  true if the clock was configured

## set_sys_clock_khz()

bool set_sys_clock_khz | ( | uint32_t | freq_khz,
|  | bool | required )

inline static

Attempt to set a system clock frequency in khz.

Note that not all clock frequencies are possible; it is preferred that you use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters for use with set_sys_clock_pll

Parameters

  freq_khz | Requested frequency
  required | if true then this function will assert if the frequency is not attainable.

Returns
  true if the clock was configured

## set_sys_clock_pll()

void set_sys_clock_pll | ( | uint32_t | vco_freq,
|  | uint | post_div1,
|  | uint | post_div2 )

Initialise the system clock.

Parameters

  vco_freq | The voltage controller oscillator frequency to be used by the SYS PLL
  post_div1 | The first post divider for the SYS PLL
  post_div2 | The second post divider for the SYS PLL.

See the PLL documentation in the datasheet for details of driving the PLLs.