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v2.2.0 (RP2040)
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pio.h
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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PIO_H
#define _HARDWARE_PIO_H
#include "pico.h"
#include "hardware/address_mapped.h"
#include "hardware/structs/pio.h"
#include "hardware/gpio.h"
#include "hardware/regs/dreq.h"
#include "hardware/pio_instructions.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO, Enable/disable assertions in the hardware_pio module, type=bool, default=0, group=hardware_pio
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO
#ifdef PARAM_ASSERTIONS_ENABLED_PIO // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO PARAM_ASSERTIONS_ENABLED_PIO
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO 0
#endif
#endif
// PICO_CONFIG: PICO_PIO_VERSION, PIO hardware version, type=int, default=0 on RP2040 and 1 on RP2350, group=hardware_pio
#ifndef PICO_PIO_VERSION
#if PIO_GPIOBASE_BITS
#define PICO_PIO_VERSION 1
#else
#define PICO_PIO_VERSION 0
#endif
#endif
// PICO_CONFIG: PICO_PIO_CLKDIV_ROUND_NEAREST, True if floating point PIO clock divisors should be rounded to the nearest possible clock divisor rather than rounding down, type=bool, default=PICO_CLKDIV_ROUND_NEAREST, group=hardware_pio
#ifndef PICO_PIO_CLKDIV_ROUND_NEAREST
#define PICO_PIO_CLKDIV_ROUND_NEAREST PICO_CLKDIV_ROUND_NEAREST
#endif
#ifdef __cplusplus
extern "C" {
#endif
static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, "");
enum pio_fifo_join {
PIO_FIFO_JOIN_NONE = 0,
PIO_FIFO_JOIN_TX = 1,
PIO_FIFO_JOIN_RX = 2,
#if PICO_PIO_VERSION > 0
PIO_FIFO_JOIN_TXGET = 4,
PIO_FIFO_JOIN_TXPUT = 8,
PIO_FIFO_JOIN_PUTGET = 12,
#endif
};
enum pio_mov_status_type {
STATUS_TX_LESSTHAN = 0,
STATUS_RX_LESSTHAN = 1,
#if PICO_PIO_VERSION > 0
STATUS_IRQ_SET = 2
#endif
};
typedef pio_hw_t *PIO;
#define pio0 pio0_hw
#define pio1 pio1_hw
#if NUM_PIOS > 2
#define pio2 pio2_hw
#endif
#if PICO_PIO_VERSION > 0
#ifndef PICO_PIO_USE_GPIO_BASE
// PICO_CONFIG: PICO_PIO_USE_GPIO_BASE, Enable code for handling more than 32 PIO pins, type=bool, default=true when supported and when the device has more than 32 pins, group=hardware_pio
#define PICO_PIO_USE_GPIO_BASE ((NUM_BANK0_GPIOS) > 32)
#endif
#endif
#ifndef PIO_NUM
static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch");
#if NUM_PIOS > 2
static_assert(PIO2_BASE - PIO0_BASE == (2u << 20), "hardware layout mismatch");
#endif
#define PIO_NUM(pio) (((uintptr_t)(pio) - PIO0_BASE) >> 20)
#endif
#ifndef PIO_INSTANCE
static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch");
#if NUM_PIOS > 2
static_assert(PIO2_BASE - PIO0_BASE == (2u << 20), "hardware layout mismatch");
#endif
#define PIO_INSTANCE(instance) ((pio_hw_t *)(PIO0_BASE + (instance) * (1u << 20)))
#endif
#ifndef PIO_FUNCSEL_NUM
#define PIO_FUNCSEL_NUM(pio, gpio) ((gpio_function_t) (GPIO_FUNC_PIO0 + PIO_NUM(pio)))
#endif
#ifndef PIO_DREQ_NUM
static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, "");
static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, "");
static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, "");
static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, "");
static_assert(DREQ_PIO1_TX0 == DREQ_PIO0_RX0 + NUM_PIO_STATE_MACHINES, "");
static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, "");
#if NUM_PIOS > 2
static_assert(DREQ_PIO2_TX0 == DREQ_PIO1_RX0 + NUM_PIO_STATE_MACHINES, "");
static_assert(DREQ_PIO2_RX0 == DREQ_PIO2_TX0 + NUM_PIO_STATE_MACHINES, "");
#endif
#define PIO_DREQ_NUM(pio, sm, is_tx) (DREQ_PIO0_TX0 + (sm) + (((is_tx) ? 0 : NUM_PIO_STATE_MACHINES) + PIO_NUM(pio) * (DREQ_PIO1_TX0 - DREQ_PIO0_TX0)))
#endif
#ifndef PIO_IRQ_NUM
#define PIO_IRQ_NUM(pio, irqn) (PIO0_IRQ_0 + NUM_PIO_IRQS * PIO_NUM(pio) + (irqn))
#endif
typedef struct {
uint32_t clkdiv;
uint32_t execctrl;
uint32_t shiftctrl;
uint32_t pinctrl;
#if PICO_PIO_USE_GPIO_BASE
#define PINHI_ALL_PINCTRL_LSBS ((1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \
(1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB))
// note we put the out_special pin starting at bit 20
#define PINHI_EXECCTRL_LSB 20
static_assert( (1u << PINHI_EXECCTRL_LSB) > (PINHI_ALL_PINCTRL_LSBS * 0x1f), "");
#define PINHI_ALL_PIN_LSBS ((1u << PINHI_EXECCTRL_LSB) |(1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \
(1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB))
// each 5-bit field which would usually be used for the pin_base in pin_ctrl, is used for:
// 0b11111 - corresponding field not specified
// 0b00000 - pin is in range 0-15
// 0b00001 - pin is in range 16-31
// 0b00010 - pin is in range 32-47
uint32_t pinhi;
#endif
} pio_sm_config;
static inline void check_sm_param(__unused uint sm) {
valid_params_if(HARDWARE_PIO, sm < NUM_PIO_STATE_MACHINES);
}
static inline void check_sm_mask(__unused uint mask) {
valid_params_if(HARDWARE_PIO, mask < (1u << NUM_PIO_STATE_MACHINES));
}
static inline void check_pio_param(__unused PIO pio) {
#if NUM_PIOS == 2
valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1);
#elif NUM_PIOS == 3
valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1 || pio == pio2);
#endif
}
static inline void check_pio_pin_param(__unused uint pin) {
#if !PICO_PIO_USE_GPIO_BASE
invalid_params_if(HARDWARE_PIO, pin >= 32);
#else
// pin base allows us to move up 16 pins at a time
invalid_params_if(HARDWARE_PIO, pin >= ((NUM_BANK0_GPIOS + 15u)&~15u));
#endif
}
static inline void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base) {
check_pio_pin_param(out_base);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_BASE_BITS) |
((out_base & 31) << PIO_SM0_PINCTRL_OUT_BASE_LSB);
#if PICO_PIO_USE_GPIO_BASE
c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_OUT_BASE_LSB)) |
((out_base >> 4) << PIO_SM0_PINCTRL_OUT_BASE_LSB);
#endif
}
static inline void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count) {
valid_params_if(HARDWARE_PIO, out_count <= 32);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_COUNT_BITS) |
(out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
}
static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) {
sm_config_set_out_pin_base(c, out_base);
sm_config_set_out_pin_count(c, out_count);
}
static inline void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base) {
check_pio_pin_param(set_base);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_BASE_BITS) |
((set_base & 31) << PIO_SM0_PINCTRL_SET_BASE_LSB);
#if PICO_PIO_USE_GPIO_BASE
c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SET_BASE_LSB)) |
((set_base >> 4) << PIO_SM0_PINCTRL_SET_BASE_LSB);
#endif
}
static inline void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count) {
valid_params_if(HARDWARE_PIO, set_count <= 5);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_COUNT_BITS) |
(set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
}
static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) {
sm_config_set_set_pin_base(c, set_base);
sm_config_set_set_pin_count(c, set_count);
}
static inline void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base) {
check_pio_pin_param(in_base);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
((in_base & 31) << PIO_SM0_PINCTRL_IN_BASE_LSB);
#if PICO_PIO_USE_GPIO_BASE
c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_IN_BASE_LSB)) |
((in_base >> 4) << PIO_SM0_PINCTRL_IN_BASE_LSB);
#endif
}
static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) {
sm_config_set_in_pin_base(c, in_base);
}
static inline void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count) {
#if PICO_PIO_VERSION == 0
// can't be changed from 32 on PIO v0
((void)c);
valid_params_if(HARDWARE_PIO, in_count == 32);
#else
valid_params_if(HARDWARE_PIO, in_count && in_count <= 32);
c->shiftctrl = (c->shiftctrl & ~PIO_SM0_SHIFTCTRL_IN_COUNT_BITS) |
((in_count & 0x1fu) << PIO_SM0_SHIFTCTRL_IN_COUNT_LSB);
#endif
}
static inline void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base) {
check_pio_pin_param(sideset_base);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
((sideset_base & 31) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
#if PICO_PIO_USE_GPIO_BASE
c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) |
((sideset_base >> 4) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
#endif
}
static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) {
sm_config_set_sideset_pin_base(c, sideset_base);
}
static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) {
valid_params_if(HARDWARE_PIO, bit_count <= 5);
valid_params_if(HARDWARE_PIO, !optional || bit_count >= 1);
c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) |
(bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB);
c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) |
(bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) |
(bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB);
}
static inline void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint32_t div_int, uint8_t div_frac8) {
static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_INT) == 16, "");
invalid_params_if(HARDWARE_PIO, div_int >> 16);
invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC) == 8, "");
c->clkdiv =
(((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
(((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
}
// backwards compatibility
static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac8) {
sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
}
static inline void pio_calculate_clkdiv8_from_float(float div, uint32_t *div_int, uint8_t *div_frac8) {
valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
const int frac_bit_count = REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC);
#if PICO_PIO_CLKDIV_ROUND_NEAREST
div += 0.5f / (1 << frac_bit_count); // round to the nearest 1/256
#endif
*div_int = (uint16_t)div;
// not a strictly necessary check, but if this changes, then this method should
// probably no longer be used in favor of one with a larger fraction
static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC) == 8, "");
if (*div_int == 0) {
*div_frac8 = 0;
} else {
*div_frac8 = (uint8_t)((div - (float)*div_int) * (1u << frac_bit_count));
}
}
// backwards compatibility
static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int16, uint8_t *div_frac8) {
uint32_t div_int;
pio_calculate_clkdiv8_from_float(div, &div_int, div_frac8);
*div_int16 = (uint16_t) div_int;
}
static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
uint32_t div_int;
uint8_t div_frac8;
pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
}
static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) {
valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT);
valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT);
c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
(wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
(wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
}
static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) {
check_pio_pin_param(pin);
c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) |
((pin & 31) << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
#if PICO_PIO_USE_GPIO_BASE
c->pinhi = (c->pinhi & ~(31u << 20)) |
((pin >> 4) << 20);
#endif
}
static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) {
valid_params_if(HARDWARE_PIO, push_threshold <= 32);
c->shiftctrl = (c->shiftctrl &
~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS |
PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS |
PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) |
(bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) |
(bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) |
((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB);
}
static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) {
valid_params_if(HARDWARE_PIO, pull_threshold <= 32);
c->shiftctrl = (c->shiftctrl &
~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS |
PIO_SM0_SHIFTCTRL_AUTOPULL_BITS |
PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) |
(bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) |
(bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) |
((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB);
}
static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) {
valid_params_if(HARDWARE_PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX
#if PICO_PIO_VERSION > 0
|| join == PIO_FIFO_JOIN_TXPUT || join == PIO_FIFO_JOIN_TXGET || join == PIO_FIFO_JOIN_PUTGET
#endif
);
#if PICO_PIO_VERSION == 0
c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) |
(((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
#else
c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS |
PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS)) |
(((uint)(join & 3)) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB) |
(((uint)(join >> 2)) << PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB);
#endif
}
static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_bit_index) {
c->execctrl = (c->execctrl &
(uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS |
PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) |
(bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) |
(bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) |
((enable_bit_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS);
}
static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) {
valid_params_if(HARDWARE_PIO,
status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN
#if PICO_PIO_VERSION > 0
|| status_sel == STATUS_IRQ_SET
#endif
);
c->execctrl = (c->execctrl
& ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
| ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS)
| ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS);
}
static inline pio_sm_config pio_get_default_sm_config(void) {
pio_sm_config c = {};
#if PICO_PIO_USE_GPIO_BASE
c.pinhi = -1;
#endif
sm_config_set_clkdiv_int_frac8(&c, 1, 0);
sm_config_set_wrap(&c, 0, 31);
sm_config_set_in_shift(&c, true, false, 32);
sm_config_set_out_shift(&c, true, false, 32);
return c;
}
static inline uint pio_get_gpio_base(PIO pio) {
#if PICO_PIO_VERSION > 0
return pio->gpiobase;
#else
((void)pio);
return 0;
#endif
}
static inline void check_pio_pin_mask64(__unused PIO pio, __unused uint sm, __unused uint64_t pinmask) {
// check no pins are set in the mask which are incompatible with the pio
#if PICO_PIO_USE_GPIO_BASE
valid_params_if(HARDWARE_PIO, (pinmask & ~(0xffffffffull << pio_get_gpio_base(pio))) == 0);
#else
valid_params_if(HARDWARE_PIO, (pinmask & ~0xffffffffull) == 0);
#endif
}
static inline int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) {
check_pio_param(pio);
check_sm_param(sm);
pio->sm[sm].clkdiv = config->clkdiv;
pio->sm[sm].shiftctrl = config->shiftctrl;
#if PICO_PIO_USE_GPIO_BASE
uint used = (~config->pinhi >> 4) & PINHI_ALL_PIN_LSBS;
// configs that use pins 0-15
uint gpio_under_16 = (~config->pinhi) & (~config->pinhi >> 1) & used;
// configs that use pins 32-47
uint gpio_over_32 = (config->pinhi >> 1) & used;
uint gpio_base = pio_get_gpio_base(pio);
invalid_params_if_and_return(PIO, gpio_under_16 && gpio_base, PICO_ERROR_BAD_ALIGNMENT);
invalid_params_if_and_return(PIO, gpio_over_32 && !gpio_base, PICO_ERROR_BAD_ALIGNMENT);
// flip the top bit of any used (execctrl/pinctrl) values to turn:
// bit6(32) + 0-15 -> base(16) + 16-31
// bit6(0) + 16-31 -> base(16) + 0-15
static_assert(PINHI_EXECCTRL_LSB == 20, ""); // we use shifts to mask off bits below
pio->sm[sm].execctrl = config->execctrl ^ (gpio_base ? ((used >> 20) << (PIO_SM0_EXECCTRL_JMP_PIN_LSB + 4)) : 0);
pio->sm[sm].pinctrl = config->pinctrl ^ (gpio_base ? ((used << 12) >> 8) : 0);
#else
pio->sm[sm].execctrl = config->execctrl;
pio->sm[sm].pinctrl = config->pinctrl;
#endif
return PICO_OK;
}
static inline uint pio_get_index(PIO pio) {
check_pio_param(pio);
return PIO_NUM(pio);
}
static inline uint pio_get_funcsel(PIO pio) {
check_pio_param(pio);
return PIO_FUNCSEL_NUM(pio, 0); // note GPIO currently unused, so won't bother updating API
}
static inline PIO pio_get_instance(uint instance) {
invalid_params_if(HARDWARE_PIO, instance >= NUM_PIOS);
return PIO_INSTANCE(instance);
}
static inline void pio_gpio_init(PIO pio, uint pin) {
check_pio_param(pio);
valid_params_if(HARDWARE_PIO, pin < NUM_BANK0_GPIOS);
gpio_set_function(pin, PIO_FUNCSEL_NUM(pio, pin));
}
static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) {
check_pio_param(pio);
check_sm_param(sm);
return PIO_DREQ_NUM(pio, sm, is_tx);
}
typedef struct pio_program {
const uint16_t *instructions;
uint8_t length;
int8_t origin; // required instruction memory origin or -1
uint8_t pio_version;
#if PICO_PIO_VERSION > 0
uint8_t used_gpio_ranges; // bitmap with one bit per 16 pins
#endif
} pio_program_t;
int pio_set_gpio_base(PIO pio, uint gpio_base);
bool pio_can_add_program(PIO pio, const pio_program_t *program);
bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
int pio_add_program(PIO pio, const pio_program_t *program);
int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset);
void pio_clear_instruction_memory(PIO pio);
int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config);
static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) {
check_pio_param(pio);
check_sm_param(sm);
pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm);
}
static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) {
check_pio_param(pio);
check_sm_mask(mask);
pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u);
}
#if PICO_PIO_VERSION > 0
static inline void pio_set_sm_multi_mask_enabled(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next, bool enabled) {
check_pio_param(pio);
check_sm_mask(mask);
pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) |
(enabled ? ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) : 0) |
(enabled ? PIO_CTRL_NEXTPREV_SM_ENABLE_BITS : PIO_CTRL_NEXTPREV_SM_DISABLE_BITS) |
((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS);
}
#endif
static inline void pio_sm_restart(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm));
}
static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
check_pio_param(pio);
check_sm_mask(mask);
hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS);
}
static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm));
}
static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
check_pio_param(pio);
check_sm_mask(mask);
hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS);
}
#if PICO_PIO_VERSION > 0
static inline void pio_clkdiv_restart_sm_multi_mask(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) {
check_pio_param(pio);
check_sm_mask(mask);
hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS |
((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS));
}
#endif
static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
check_pio_param(pio);
check_sm_mask(mask);
hw_set_bits(&pio->ctrl,
((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS));
}
#if PICO_PIO_VERSION > 0
static inline void pio_enable_sm_multi_mask_in_sync(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) {
check_pio_param(pio);
check_sm_mask(mask);
check_pio_param(pio);
check_sm_mask(mask);
hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) |
PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | PIO_CTRL_NEXTPREV_SM_ENABLE_BITS |
((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS));
}
#endif
typedef enum pio_interrupt_source {
pis_interrupt0 = PIO_INTR_SM0_LSB,
pis_interrupt1 = PIO_INTR_SM1_LSB,
pis_interrupt2 = PIO_INTR_SM2_LSB,
pis_interrupt3 = PIO_INTR_SM3_LSB,
#if PICO_PIO_VERSION > 0
pis_interrupt4 = PIO_INTR_SM4_LSB,
pis_interrupt5 = PIO_INTR_SM5_LSB,
pis_interrupt6 = PIO_INTR_SM6_LSB,
pis_interrupt7 = PIO_INTR_SM7_LSB,
#endif
pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB,
pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB,
pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB,
pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB,
pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB,
pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB,
pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB,
pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB,
} pio_interrupt_source_t;
static inline void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) {
check_pio_param(pio);
invalid_params_if(HARDWARE_PIO, source >= 32u || (1u << source) > PIO_INTR_BITS);
if (enabled)
hw_set_bits(&pio->inte0, 1u << source);
else
hw_clear_bits(&pio->inte0, 1u << source);
}
static inline void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) {
check_pio_param(pio);
invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS);
if (enabled)
hw_set_bits(&pio->inte1, 1u << source);
else
hw_clear_bits(&pio->inte1, 1u << source);
}
static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
check_pio_param(pio);
invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
if (enabled) {
hw_set_bits(&pio->inte0, source_mask);
} else {
hw_clear_bits(&pio->inte0, source_mask);
}
}
static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
check_pio_param(pio);
invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
if (enabled) {
hw_set_bits(&pio->inte1, source_mask);
} else {
hw_clear_bits(&pio->inte1, source_mask);
}
}
static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled) {
invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS);
invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS);
if (enabled)
hw_set_bits(&pio->irq_ctrl[irq_index].inte, 1u << source);
else
hw_clear_bits(&pio->irq_ctrl[irq_index].inte, 1u << source);
}
static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) {
invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS);
static_assert(NUM_PIO_IRQS == 2, "");
invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
if (enabled) {
hw_set_bits(&pio->irq_ctrl[irq_index].inte, source_mask);
} else {
hw_clear_bits(&pio->irq_ctrl[irq_index].inte, source_mask);
}
}
static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
check_pio_param(pio);
invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8);
return pio->irq & (1u << pio_interrupt_num);
}
static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
check_pio_param(pio);
invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8);
pio->irq = (1u << pio_interrupt_num);
}
static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return (uint8_t) pio->sm[sm].addr;
}
inline static void pio_sm_exec(PIO pio, uint sm, uint instr) {
check_pio_param(pio);
check_sm_param(sm);
pio->sm[sm].instr = instr;
}
static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS;
}
static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) {
check_pio_param(pio);
check_sm_param(sm);
pio_sm_exec(pio, sm, instr);
while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents();
}
static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) {
check_pio_param(pio);
check_sm_param(sm);
valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT);
valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT);
pio->sm[sm].execctrl =
(pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
(wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
(wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
}
static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) {
check_pio_param(pio);
check_sm_param(sm);
#if PICO_PIO_USE_GPIO_BASE
out_base -= pio_get_gpio_base(pio);
#endif
valid_params_if(HARDWARE_PIO, out_base < 32);
valid_params_if(HARDWARE_PIO, out_count <= 32);
pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
(out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
(out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
}
static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) {
check_pio_param(pio);
check_sm_param(sm);
#if PICO_PIO_USE_GPIO_BASE
set_base -= pio_get_gpio_base(pio);
#endif
valid_params_if(HARDWARE_PIO, set_base < 32);
valid_params_if(HARDWARE_PIO, set_count <= 5);
pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
(set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
(set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
}
static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) {
check_pio_param(pio);
check_sm_param(sm);
#if PICO_PIO_USE_GPIO_BASE
in_base -= pio_get_gpio_base(pio);
#endif
valid_params_if(HARDWARE_PIO, in_base < 32);
pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
(in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
}
static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) {
check_pio_param(pio);
check_sm_param(sm);
#if PICO_PIO_USE_GPIO_BASE
sideset_base -= pio_get_gpio_base(pio);
#endif
valid_params_if(HARDWARE_PIO, sideset_base < 32);
pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
(sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
}
static inline void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin) {
check_pio_param(pio);
check_sm_param(sm);
#if PICO_PIO_USE_GPIO_BASE
pin -= pio_get_gpio_base(pio);
#endif
valid_params_if(HARDWARE_PIO, pin < 32);
pio->sm[sm].execctrl =
(pio->sm[sm].execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS)
| (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
}
static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) {
check_pio_param(pio);
check_sm_param(sm);
pio->txf[sm] = data;
}
static inline uint32_t pio_sm_get(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return pio->rxf[sm];
}
static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0;
}
static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0;
}
static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB);
const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB;
return (pio->flevel >> bitoffs) & mask;
}
static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0;
}
static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0;
}
static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB);
const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB;
return (pio->flevel >> bitoffs) & mask;
}
static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) {
check_pio_param(pio);
check_sm_param(sm);
while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents();
pio_sm_put(pio, sm, data);
}
static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) {
check_pio_param(pio);
check_sm_param(sm);
while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents();
return pio_sm_get(pio, sm);
}
void pio_sm_drain_tx_fifo(PIO pio, uint sm);
static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint32_t div_int, uint8_t div_frac8) {
check_pio_param(pio);
check_sm_param(sm);
static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_INT) == 16, "");
invalid_params_if(HARDWARE_PIO, div_int >> 16);
invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC) == 8, "");
pio->sm[sm].clkdiv =
(((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
(((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
}
// backwards compatibility
static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac8) {
pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
}
static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
check_pio_param(pio);
check_sm_param(sm);
uint32_t div_int;
uint8_t div_frac8;
pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
}
static inline void pio_sm_clear_fifos(PIO pio, uint sm) {
// changing the FIFO join state clears the fifo
check_pio_param(pio);
check_sm_param(sm);
hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
}
void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values);
void pio_sm_set_pins64(PIO pio, uint sm, uint64_t pin_values);
void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask);
void pio_sm_set_pins_with_mask64(PIO pio, uint sm, uint64_t pin_values, uint64_t pin_mask);
void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask);
void pio_sm_set_pindirs_with_mask64(PIO pio, uint sm, uint64_t pin_dirs, uint64_t pin_mask);
int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out);
void pio_sm_claim(PIO pio, uint sm);
void pio_claim_sm_mask(PIO pio, uint sm_mask);
void pio_sm_unclaim(PIO pio, uint sm);
int pio_claim_unused_sm(PIO pio, bool required);
bool pio_sm_is_claimed(PIO pio, uint sm);
bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset);
bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base);
void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset);
static inline int pio_get_irq_num(PIO pio, uint irqn) {
check_pio_param(pio);
valid_params_if(HARDWARE_PIO, irqn < NUM_PIO_IRQS);
return PIO_IRQ_NUM(pio, irqn);
}
static inline pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm) {
check_sm_param(sm);
return ((pio_interrupt_source_t)(pis_sm0_tx_fifo_not_full + sm));
}
static inline pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm) {
check_sm_param(sm);
return ((pio_interrupt_source_t)(pis_sm0_rx_fifo_not_empty + sm));
}
#ifdef __cplusplus
}
#endif
#endif // _PIO_H_
address_mapped.h
gpio.h
hw_set_bits
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition address_mapped.h:135
hw_xor_bits
static __force_inline void hw_xor_bits(io_rw_32 *addr, uint32_t mask)
Atomically flip the specified bits in a HW register.
Definition address_mapped.h:155
hw_clear_bits
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition address_mapped.h:145
DREQ_PIO0_TX3
@ DREQ_PIO0_TX3
Select PIO0's TX FIFO 3 as DREQ.
Definition dreq.h:70
DREQ_PIO1_TX0
@ DREQ_PIO1_TX0
Select PIO1's TX FIFO 0 as DREQ.
Definition dreq.h:75
DREQ_PIO1_RX0
@ DREQ_PIO1_RX0
Select PIO1's RX FIFO 0 as DREQ.
Definition dreq.h:79
DREQ_PIO0_TX2
@ DREQ_PIO0_TX2
Select PIO0's TX FIFO 2 as DREQ.
Definition dreq.h:69
DREQ_PIO0_RX0
@ DREQ_PIO0_RX0
Select PIO0's RX FIFO 0 as DREQ.
Definition dreq.h:71
DREQ_PIO0_TX1
@ DREQ_PIO0_TX1
Select PIO0's TX FIFO 1 as DREQ.
Definition dreq.h:68
DREQ_PIO0_TX0
@ DREQ_PIO0_TX0
Select PIO0's TX FIFO 0 as DREQ.
Definition dreq.h:67
gpio_set_function
void gpio_set_function(uint gpio, gpio_function_t fn)
Select GPIO function.
Definition gpio.c:38
pio_sm_get_tx_fifo_level
static uint pio_sm_get_tx_fifo_level(PIO pio, uint sm)
Return the number of elements currently in a state machine's TX FIFO.
Definition pio.h:1725
pio_claim_free_sm_and_add_program
bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset)
Finds a PIO and statemachine and adds a program into PIO memory.
Definition pio.c:404
PIO_INSTANCE
#define PIO_INSTANCE(instance)
Returns the PIO instance with the given PIO number.
Definition pio.h:194
pio_set_irqn_source_enabled
static void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's specified (0/1) IRQ index.
Definition pio.h:1367
pio_sm_set_pins_with_mask64
void pio_sm_set_pins_with_mask64(PIO pio, uint sm, uint64_t pin_values, uint64_t pin_mask)
Use a state machine to set a value on multiple pins for the PIO instance.
Definition pio.c:298
pio_interrupt_source
pio_interrupt_source
PIO interrupt source numbers for pio related IRQs.
Definition pio.h:1272
pio_sm_get_blocking
static uint32_t pio_sm_get_blocking(PIO pio, uint sm)
Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty.
Definition pio.h:1753
pio_sm_set_pins
void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values)
Use a state machine to set a value on all pins for the PIO instance.
Definition pio.c:230
pio_add_program_at_offset
int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset)
Attempt to load the program at the specified instruction memory offset.
Definition pio.c:192
pio_sm_set_clkdiv_int_frac8
static void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint32_t div_int, uint8_t div_frac8)
set the current clock divider for a state machine using a 16:8 fraction
Definition pio.h:1783
pio_get_instance
static PIO pio_get_instance(uint instance)
Convert PIO instance to hardware instance.
Definition pio.h:865
pio_sm_exec_wait_blocking
static void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr)
Immediately execute an instruction on a state machine and wait for it to complete.
Definition pio.h:1476
pio_sm_set_config
static int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config)
Apply a state machine configuration to a state machine.
Definition pio.h:809
pio_get_irq_num
static int pio_get_irq_num(PIO pio, uint irqn)
Return an IRQ for a PIO hardware instance.
Definition pio.h:2047
pio_set_gpio_base
int pio_set_gpio_base(PIO pio, uint gpio_base)
Set the base GPIO base for the PIO instance.
Definition pio.c:97
pio_mov_status_type
pio_mov_status_type
MOV status types.
Definition pio.h:122
pio_sm_is_tx_fifo_full
static bool pio_sm_is_tx_fifo_full(PIO pio, uint sm)
Determine if a state machine's TX FIFO is full.
Definition pio.h:1699
pio_get_dreq
static uint pio_get_dreq(PIO pio, uint sm, bool is_tx)
Return the DREQ to use for pacing transfers to/from a particular state machine FIFO.
Definition pio.h:911
pio_set_irq1_source_enabled
static void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's IRQ 1.
Definition pio.h:1316
pio_sm_set_pindirs_with_mask64
void pio_sm_set_pindirs_with_mask64(PIO pio, uint sm, uint64_t pin_dirs, uint64_t pin_mask)
Use a state machine to set the pin directions for multiple pins for the PIO instance.
Definition pio.c:335
pio_sm_drain_tx_fifo
void pio_sm_drain_tx_fifo(PIO pio, uint sm)
Empty out a state machine's TX FIFO.
Definition pio.c:396
pio_claim_sm_mask
void pio_claim_sm_mask(PIO pio, uint sm_mask)
Mark multiple state machines as used.
Definition pio.c:36
pio_claim_free_sm_and_add_program_for_gpio_range
bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base)
Finds a PIO and statemachine and adds a program into PIO memory.
Definition pio.c:408
pio_sm_set_pins64
void pio_sm_set_pins64(PIO pio, uint sm, uint64_t pin_values)
Use a state machine to set a value on all pins for the PIO instance.
Definition pio.c:261
pio_claim_unused_sm
int pio_claim_unused_sm(PIO pio, bool required)
Claim a free state machine on a PIO instance.
Definition pio.c:48
pio_sm_unclaim
void pio_sm_unclaim(PIO pio, uint sm)
Mark a state machine as no longer used.
Definition pio.c:42
pio_clkdiv_restart_sm_mask
static void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask)
Restart multiple state machines' clock dividers from a phase of 0.
Definition pio.h:1175
pio_sm_is_claimed
bool pio_sm_is_claimed(PIO pio, uint sm)
Determine if a PIO state machine is claimed.
Definition pio.c:57
pio_interrupt_clear
static void pio_interrupt_clear(PIO pio, uint pio_interrupt_num)
Clear a particular PIO interrupt.
Definition pio.h:1414
pio_sm_get
static uint32_t pio_sm_get(PIO pio, uint sm)
Read a word of data from a state machine's RX FIFO.
Definition pio.h:1645
pio_sm_is_rx_fifo_full
static bool pio_sm_is_rx_fifo_full(PIO pio, uint sm)
Determine if a state machine's RX FIFO is full.
Definition pio.h:1658
pio_sm_set_wrap
static void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap)
Set the current wrap configuration for a state machine.
Definition pio.h:1492
PIO_NUM
#define PIO_NUM(pio)
Returns the PIO number for a PIO instance.
Definition pio.h:178
pio_sm_restart
static void pio_sm_restart(PIO pio, uint sm)
Restart a state machine with a known state.
Definition pio.h:1098
pio_fifo_join
pio_fifo_join
FIFO join states.
Definition pio.h:108
pio_sm_set_out_pins
static void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count)
Set the current 'out' pins for a state machine.
Definition pio.h:1513
pio_sm_exec
static void pio_sm_exec(PIO pio, uint sm, uint instr)
Immediately execute an instruction on a state machine.
Definition pio.h:1445
pio_set_irq0_source_mask_enabled
static void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's IRQ 0.
Definition pio.h:1332
pio_remove_program
void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset)
Remove a program from a PIO instance's instruction memory.
Definition pio.c:199
pio_sm_set_pindirs_with_mask
void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask)
Use a state machine to set the pin directions for multiple pins for the PIO instance.
Definition pio.c:307
pio_clear_instruction_memory
void pio_clear_instruction_memory(PIO pio)
Clears all of a PIO instance's instruction memory.
Definition pio.c:208
pio_sm_set_sideset_pins
static void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base)
Set the current 'sideset' pins for a state machine.
Definition pio.h:1579
pio_sm_set_clkdiv
static void pio_sm_set_clkdiv(PIO pio, uint sm, float div)
set the current clock divider for a state machine
Definition pio.h:1807
pio_get_gpio_base
static uint pio_get_gpio_base(PIO pio)
Return the base GPIO base for the PIO instance.
Definition pio.h:780
pio_get_tx_fifo_not_full_interrupt_source
static pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm)
Return the interrupt source for a state machines TX FIFO not full interrupt.
Definition pio.h:2059
pio_sm_init
int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config)
Resets the state machine to a consistent state, and configures it.
Definition pio.c:365
pio_sm_get_rx_fifo_level
static uint pio_sm_get_rx_fifo_level(PIO pio, uint sm)
Return the number of elements currently in a state machine's RX FIFO.
Definition pio.h:1684
pio0
#define pio0
Definition pio.h:138
pio1
#define pio1
Definition pio.h:146
pio_sm_set_pins_with_mask
void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask)
Use a state machine to set a value on multiple pins for the PIO instance.
Definition pio.c:270
pio_sm_set_jmp_pin
static void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin)
Set the 'jmp' pin for a state machine.
Definition pio.h:1598
pio_sm_get_pc
static uint8_t pio_sm_get_pc(PIO pio, uint sm)
Return the current program counter for a state machine.
Definition pio.h:1427
pio_get_funcsel
static uint pio_get_funcsel(PIO pio)
Return the funcsel number of a PIO instance.
Definition pio.h:854
PIO_FUNCSEL_NUM
#define PIO_FUNCSEL_NUM(pio, gpio)
Returns gpio_function_t needed to select the PIO function for the given PIO instance on the given GPI...
Definition pio.h:206
pio_sm_set_enabled
static void pio_sm_set_enabled(PIO pio, uint sm, bool enabled)
Enable or disable a PIO state machine.
Definition pio.h:1036
pio_sm_claim
void pio_sm_claim(PIO pio, uint sm)
Mark a state machine as used.
Definition pio.c:24
pio_remove_program_and_unclaim_sm
void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset)
Removes a program from PIO memory and unclaims the state machine.
Definition pio.c:464
pio_can_add_program
bool pio_can_add_program(PIO pio, const pio_program_t *program)
Determine whether the given program can (at the time of the call) be loaded onto the PIO instance.
Definition pio.c:145
pio_interrupt_get
static bool pio_interrupt_get(PIO pio, uint pio_interrupt_num)
Determine if a particular PIO interrupt is set.
Definition pio.h:1402
pio_sm_is_exec_stalled
static bool pio_sm_is_exec_stalled(PIO pio, uint sm)
Determine if an instruction set by pio_sm_exec() is stalled executing.
Definition pio.h:1458
pio_can_add_program_at_offset
bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset)
Determine whether the given program can (at the time of the call) be loaded onto the PIO instance sta...
Definition pio.c:153
pio_sm_put
static void pio_sm_put(PIO pio, uint sm, uint32_t data)
Write a word of data to a state machine's TX FIFO.
Definition pio.h:1624
pio_sm_clear_fifos
static void pio_sm_clear_fifos(PIO pio, uint sm)
Clear a state machine's TX and RX FIFOs.
Definition pio.h:1822
pio_interrupt_source_t
enum pio_interrupt_source pio_interrupt_source_t
PIO interrupt source numbers for pio related IRQs.
PIO_DREQ_NUM
#define PIO_DREQ_NUM(pio, sm, is_tx)
Returns the dreq_num_t used for pacing DMA transfers to or from a given state machine's FIFOs on this...
Definition pio.h:229
pio_enable_sm_mask_in_sync
static void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask)
Enable multiple PIO state machines synchronizing their clock dividers.
Definition pio.h:1234
pio_sm_set_set_pins
static void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count)
Set the current 'set' pins for a state machine.
Definition pio.h:1537
pio_sm_clkdiv_restart
static void pio_sm_clkdiv_restart(PIO pio, uint sm)
Restart a state machine's clock divider from a phase of 0.
Definition pio.h:1140
pio_get_rx_fifo_not_empty_interrupt_source
static pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm)
Return the interrupt source for a state machines RX FIFO not empty interrupt.
Definition pio.h:2070
pio_sm_is_rx_fifo_empty
static bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm)
Determine if a state machine's RX FIFO is empty.
Definition pio.h:1671
pio_sm_is_tx_fifo_empty
static bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm)
Determine if a state machine's TX FIFO is empty.
Definition pio.h:1712
pio_set_irq1_source_mask_enabled
static void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's IRQ 1.
Definition pio.h:1349
pio_restart_sm_mask
static void pio_restart_sm_mask(PIO pio, uint32_t mask)
Restart multiple state machine with a known state.
Definition pio.h:1113
pio_get_index
static uint pio_get_index(PIO pio)
Return the instance number of a PIO instance.
Definition pio.h:842
PIO_IRQ_NUM
#define PIO_IRQ_NUM(pio, irqn)
Returns the irq_num_t for processor interrupts from the given PIO instance.
Definition pio.h:241
pio_sm_put_blocking
static void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data)
Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full.
Definition pio.h:1740
pio_sm_set_in_pins
static void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base)
Set the current 'in' pins for a state machine.
Definition pio.h:1559
pio_add_program
int pio_add_program(PIO pio, const pio_program_t *program)
Attempt to load the program.
Definition pio.c:182
pio_sm_set_consecutive_pindirs
int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out)
Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance.
Definition pio.c:343
pio_set_sm_mask_enabled
static void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled)
Enable or disable multiple PIO state machines.
Definition pio.h:1055
pio_gpio_init
static void pio_gpio_init(PIO pio, uint pin)
Setup the function select for a GPIO to use output from the given PIO instance.
Definition pio.h:898
pio_set_irqn_source_mask_enabled
static void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index.
Definition pio.h:1384
pio_set_irq0_source_enabled
static void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's IRQ 0.
Definition pio.h:1300
pis_interrupt2
@ pis_interrupt2
PIO interrupt 2 is raised.
Definition pio.h:1275
pis_sm2_tx_fifo_not_full
@ pis_sm2_tx_fifo_not_full
State machine 2 TX FIFO is not full.
Definition pio.h:1285
pis_interrupt0
@ pis_interrupt0
PIO interrupt 0 is raised.
Definition pio.h:1273
pis_sm1_tx_fifo_not_full
@ pis_sm1_tx_fifo_not_full
State machine 1 TX FIFO is not full.
Definition pio.h:1284
pis_sm3_tx_fifo_not_full
@ pis_sm3_tx_fifo_not_full
State machine 3 TX FIFO is not full.
Definition pio.h:1286
pis_interrupt1
@ pis_interrupt1
PIO interrupt 1 is raised.
Definition pio.h:1274
pis_sm2_rx_fifo_not_empty
@ pis_sm2_rx_fifo_not_empty
State machine 2 RX FIFO is not empty.
Definition pio.h:1289
pis_sm1_rx_fifo_not_empty
@ pis_sm1_rx_fifo_not_empty
State machine 1 RX FIFO is not empty.
Definition pio.h:1288
pis_sm0_tx_fifo_not_full
@ pis_sm0_tx_fifo_not_full
State machine 0 TX FIFO is not full.
Definition pio.h:1283
pis_interrupt3
@ pis_interrupt3
PIO interrupt 3 is raised.
Definition pio.h:1276
pis_sm0_rx_fifo_not_empty
@ pis_sm0_rx_fifo_not_empty
State machine 0 RX FIFO is not empty.
Definition pio.h:1287
pis_sm3_rx_fifo_not_empty
@ pis_sm3_rx_fifo_not_empty
State machine 3 RX FIFO is not empty.
Definition pio.h:1290
PIO_FIFO_JOIN_NONE
@ PIO_FIFO_JOIN_NONE
TX FIFO length=4 is used for transmit, RX FIFO length=4 is used for receive.
Definition pio.h:109
PIO_FIFO_JOIN_TX
@ PIO_FIFO_JOIN_TX
TX FIFO length=8 is used for transmit, RX FIFO is disabled.
Definition pio.h:110
PIO_FIFO_JOIN_RX
@ PIO_FIFO_JOIN_RX
RX FIFO length=8 is used for receive, TX FIFO is disabled.
Definition pio.h:111
PICO_OK
@ PICO_OK
No error; the operation succeeded.
Definition error.h:23
PICO_ERROR_BAD_ALIGNMENT
@ PICO_ERROR_BAD_ALIGNMENT
Address was mis-aligned (usually not on word boundary).
Definition error.h:35
tight_loop_contents
static __force_inline void tight_loop_contents(void)
No-op function for the body of tight loops.
Definition common.h:74
sm_config_set_out_pin_base
static void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base)
Set the base of the 'out' pins in a state machine configuration.
Definition pio.h:345
sm_config_set_out_special
static void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_bit_index)
Set special 'out' operations in a state machine configuration.
Definition pio.h:710
sm_config_set_set_pin_base
static void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base)
Set the base of the 'set' pins in a state machine configuration.
Definition pio.h:391
sm_config_set_in_pin_count
static void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count)
Set the count of 'in' pins in a state machine configuration.
Definition pio.h:472
sm_config_set_out_shift
static void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold)
Setup 'out' shifting parameters in a state machine configuration.
Definition pio.h:668
sm_config_set_set_pin_count
static void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count)
Set the count of 'set' pins in a state machine configuration.
Definition pio.h:409
sm_config_set_sideset_pin_base
static void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base)
Set the base of the 'sideset' pins in a state machine configuration.
Definition pio.h:492
sm_config_set_clkdiv_int_frac8
static void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint32_t div_int, uint8_t div_frac8)
Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine con...
Definition pio.h:548
sm_config_set_in_pin_base
static void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base)
Set the base of the 'in' pins in a state machine configuration.
Definition pio.h:437
sm_config_set_in_pins
static void sm_config_set_in_pins(pio_sm_config *c, uint in_base)
Set the base for the 'in' pins in a state machine configuration.
Definition pio.h:455
sm_config_set_mov_status
static void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n)
Set source for 'mov status' in a state machine configuration.
Definition pio.h:726
sm_config_set_sideset_pins
static void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base)
Set the 'sideset' pins in a state machine configuration.
Definition pio.h:513
sm_config_set_set_pins
static void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count)
Set the 'set' pins in a state machine configuration.
Definition pio.h:424
sm_config_set_out_pin_count
static void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count)
Set the number of 'out' pins in a state machine configuration.
Definition pio.h:363
sm_config_set_clkdiv
static void sm_config_set_clkdiv(pio_sm_config *c, float div)
Set the state machine clock divider (from a floating point value) in a state machine configuration.
Definition pio.h:602
sm_config_set_in_shift
static void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold)
Setup 'in' shifting parameters in a state machine configuration.
Definition pio.h:649
sm_config_set_jmp_pin
static void sm_config_set_jmp_pin(pio_sm_config *c, uint pin)
Set the 'jmp' pin in a state machine configuration.
Definition pio.h:631
pio_get_default_sm_config
static pio_sm_config pio_get_default_sm_config(void)
Get the default state machine configuration.
Definition pio.h:758
sm_config_set_out_pins
static void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count)
Set the 'out' pins in a state machine configuration.
Definition pio.h:378
sm_config_set_sideset
static void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs)
Set the 'sideset' options in a state machine configuration.
Definition pio.h:525
sm_config_set_wrap
static void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap)
Set the wrap addresses in a state machine configuration.
Definition pio.h:617
sm_config_set_fifo_join
static void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join)
Setup the FIFO joining in a state machine configuration.
Definition pio.h:685
pico.h
pio_hw_t
Definition pio.h:132
pio_program
Definition pio.h:917
pio_sm_config
PIO Configuration structure.
Definition pio.h:290