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v2.2.0 (RP2040)
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dma.h
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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_DMA_H
#define _HARDWARE_DMA_H
#include "pico.h"
#include "hardware/structs/dma.h"
#include "hardware/regs/dreq.h"
#include "pico/assert.h"
#include "hardware/regs/intctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA, Enable/disable hardware_dma assertions, type=bool, default=0, group=hardware_dma
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA
#ifdef PARAM_ASSERTIONS_ENABLED_DMA // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA PARAM_ASSERTIONS_ENABLED_DMA
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA 0
#endif
#endif
#ifndef DMA_IRQ_NUM
#define DMA_IRQ_NUM(irq_index) (DMA_IRQ_0 + (irq_index))
#endif
static inline void check_dma_channel_param(__unused uint channel) {
#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA)
// this method is used a lot by inline functions so avoid code bloat by deferring to function
extern void check_dma_channel_param_impl(uint channel);
check_dma_channel_param_impl(channel);
#endif
}
static inline void check_dma_timer_param(__unused uint timer_num) {
valid_params_if(HARDWARE_DMA, timer_num < NUM_DMA_TIMERS);
}
inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
check_dma_channel_param(channel);
return &dma_hw->ch[channel];
}
void dma_channel_claim(uint channel);
void dma_claim_mask(uint32_t channel_mask);
void dma_channel_unclaim(uint channel);
void dma_unclaim_mask(uint32_t channel_mask);
int dma_claim_unused_channel(bool required);
bool dma_channel_is_claimed(uint channel);
typedef enum dma_channel_transfer_size {
DMA_SIZE_8 = 0,
DMA_SIZE_16 = 1,
DMA_SIZE_32 = 2
} dma_channel_transfer_size_t;
typedef enum dma_address_update_type {
DMA_ADDRESS_UPDATE_NONE = 0,
DMA_ADDRESS_UPDATE_INCREMENT = 1,
#if !PICO_RP2040
DMA_ADDRESS_UPDATE_INCREMENT_BY_TWO = 2,
DMA_ADDRESS_UPDATE_DECREMENT = 3,
#endif
} dma_address_update_type_t;
typedef struct {
uint32_t ctrl;
} dma_channel_config_t;
// backwards compatibility
typedef dma_channel_config_t dma_channel_config;
#ifndef DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_READ_BITS
#if PICO_RP2040
#define DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_READ_BITS(u) (((u)&1) << DMA_CH0_CTRL_TRIG_INCR_READ_LSB)
#else
#define DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_READ_BITS(u) \
((((u)&1) << DMA_CH0_CTRL_TRIG_INCR_READ_LSB) | \
(((u)&2) << (DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB - 1)))
#endif
#endif
#ifndef DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_WRITE_BITS
#if PICO_RP2040
#define DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_WRITE_BITS(u) (((u)&1) << DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB)
#else
#define DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_WRITE_BITS(u) \
((((u)&1) << DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB) | \
(((u)&2) << (DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB - 1)))
#endif
#endif
#ifndef DMA_CH_CTRL_ALL_ADDRESS_UPDATE_READ_BITS
#if PICO_RP2040
#define DMA_CH_CTRL_ALL_ADDRESS_UPDATE_READ_BITS DMA_CH0_CTRL_TRIG_INCR_READ_BITS
#else
#define DMA_CH_CTRL_ALL_ADDRESS_UPDATE_READ_BITS (DMA_CH0_CTRL_TRIG_INCR_READ_BITS | DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS)
#endif
#endif
#ifndef DMA_CH_CTRL_ALL_ADDRESS_UPDATE_WRITE_BITS
#if PICO_RP2040
#define DMA_CH_CTRL_ALL_ADDRESS_UPDATE_WRITE_BITS DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS
#else
#define DMA_CH_CTRL_ALL_ADDRESS_UPDATE_WRITE_BITS (DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS | DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS)
#endif
#endif
static inline void channel_config_set_read_address_update_type(dma_channel_config_t *c, dma_address_update_type_t update_type) {
c->ctrl = (c->ctrl & ~DMA_CH_CTRL_ALL_ADDRESS_UPDATE_READ_BITS) |
DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_READ_BITS(update_type);
}
static inline void channel_config_set_write_address_update_type(dma_channel_config_t *c, dma_address_update_type_t update_type) {
c->ctrl = (c->ctrl & ~DMA_CH_CTRL_ALL_ADDRESS_UPDATE_WRITE_BITS) |
DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_WRITE_BITS(update_type);
}
static inline void channel_config_set_read_increment(dma_channel_config_t *c, bool incr) {
channel_config_set_read_address_update_type(c, incr ? DMA_ADDRESS_UPDATE_INCREMENT : DMA_ADDRESS_UPDATE_NONE);
}
static inline void channel_config_set_write_increment(dma_channel_config_t *c, bool incr) {
channel_config_set_write_address_update_type(c, incr ? DMA_ADDRESS_UPDATE_INCREMENT : DMA_ADDRESS_UPDATE_NONE);
}
static inline void channel_config_set_dreq(dma_channel_config_t *c, uint dreq) {
assert(dreq <= DREQ_FORCE);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB);
}
static inline void channel_config_set_chain_to(dma_channel_config_t *c, uint chain_to) {
assert(chain_to <= NUM_DMA_CHANNELS);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB);
}
static inline void channel_config_set_transfer_data_size(dma_channel_config_t *c, dma_channel_transfer_size_t size) {
assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
}
static inline void channel_config_set_ring(dma_channel_config_t *c, bool write, uint size_bits) {
assert(size_bits < 32);
c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) |
(size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) |
(write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0);
}
static inline void channel_config_set_bswap(dma_channel_config_t *c, bool bswap) {
c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS);
}
static inline void channel_config_set_irq_quiet(dma_channel_config_t *c, bool irq_quiet) {
c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
}
static inline void channel_config_set_high_priority(dma_channel_config_t *c, bool high_priority) {
c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS);
}
static inline void channel_config_set_enable(dma_channel_config_t *c, bool enable) {
c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS);
}
static inline void channel_config_set_sniff_enable(dma_channel_config_t *c, bool sniff_enable) {
c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl &
~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
}
static inline dma_channel_config_t dma_channel_get_default_config(uint channel) {
dma_channel_config_t c = {0};
channel_config_set_read_increment(&c, true);
channel_config_set_write_increment(&c, false);
channel_config_set_dreq(&c, DREQ_FORCE);
channel_config_set_chain_to(&c, channel);
channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
channel_config_set_ring(&c, false, 0);
channel_config_set_bswap(&c, false);
channel_config_set_irq_quiet(&c, false);
channel_config_set_enable(&c, true);
channel_config_set_sniff_enable(&c, false);
channel_config_set_high_priority( &c, false);
return c;
}
static inline dma_channel_config_t dma_get_channel_config(uint channel) {
dma_channel_config_t c;
c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig;
return c;
}
static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config_t *config) {
return config->ctrl;
}
static inline void dma_channel_set_config(uint channel, const dma_channel_config_t *config, bool trigger) {
// Don't use CTRL_TRIG since we don't want to start a transfer
if (!trigger) {
dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config);
} else {
dma_channel_hw_addr(channel)->ctrl_trig = channel_config_get_ctrl_value(config);
}
}
static inline void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger) {
if (!trigger) {
dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr;
} else {
dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr;
}
}
static inline void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger) {
if (!trigger) {
dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr;
} else {
dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr;
}
}
static inline uint32_t dma_encode_transfer_count(uint transfer_count) {
#if !PICO_RP2040
invalid_params_if(HARDWARE_DMA, transfer_count & DMA_CH0_TRANS_COUNT_MODE_BITS);
return transfer_count & DMA_CH0_TRANS_COUNT_COUNT_BITS;
#else
return transfer_count;
#endif
}
static inline uint32_t dma_encode_transfer_count_with_self_trigger(uint transfer_count) {
#if PICO_RP2040
panic_unsupported();
#else
return dma_encode_transfer_count(transfer_count) | (DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF << DMA_CH0_TRANS_COUNT_MODE_LSB);
#endif
}
static inline uint32_t dma_encode_endless_transfer_count(void) {
#if PICO_RP2040
panic_unsupported();
#else
static_assert(DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS == 0xf);
static_assert(DMA_CH0_TRANS_COUNT_MODE_LSB == 28);
return 0xffffffffu;
#endif
}
static inline void dma_channel_set_transfer_count(uint channel, uint32_t encoded_transfer_count, bool trigger) {
if (!trigger) {
dma_channel_hw_addr(channel)->transfer_count = encoded_transfer_count;
} else {
dma_channel_hw_addr(channel)->al1_transfer_count_trig = encoded_transfer_count;
}
}
// backwards compatibility with SDK < 2.2.0
static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger) {
dma_channel_set_transfer_count(channel, trans_count, trigger);
}
static inline void dma_channel_configure(uint channel, const dma_channel_config_t *config, volatile void *write_addr,
const volatile void *read_addr,
uint32_t encoded_transfer_count, bool trigger) {
dma_channel_set_read_addr(channel, read_addr, false);
dma_channel_set_write_addr(channel, write_addr, false);
dma_channel_set_transfer_count(channel, encoded_transfer_count, false);
dma_channel_set_config(channel, config, trigger);
}
inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel,
const volatile void *read_addr,
uint32_t encoded_transfer_count) {
// check_dma_channel_param(channel);
dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
hw->read_addr = (uintptr_t) read_addr;
hw->al1_transfer_count_trig = encoded_transfer_count;
}
inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t encoded_transfer_count) {
dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
hw->write_addr = (uintptr_t) write_addr;
hw->al1_transfer_count_trig = encoded_transfer_count;
}
static inline void dma_start_channel_mask(uint32_t chan_mask) {
valid_params_if(HARDWARE_DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS));
dma_hw->multi_channel_trigger = chan_mask;
}
static inline void dma_channel_start(uint channel) {
dma_start_channel_mask(1u << channel);
}
static inline void dma_channel_abort(uint channel) {
check_dma_channel_param(channel);
dma_hw->abort = 1u << channel;
// Bit will go 0 once channel has reached safe state
// (i.e. any in-flight transfers have retired)
while (dma_hw->ch[channel].ctrl_trig & DMA_CH0_CTRL_TRIG_BUSY_BITS) tight_loop_contents();
}
static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) {
check_dma_channel_param(channel);
check_hw_layout(dma_hw_t, inte0, DMA_INTE0_OFFSET);
if (enabled)
hw_set_bits(&dma_hw->inte0, 1u << channel);
else
hw_clear_bits(&dma_hw->inte0, 1u << channel);
}
static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
if (enabled) {
hw_set_bits(&dma_hw->inte0, channel_mask);
} else {
hw_clear_bits(&dma_hw->inte0, channel_mask);
}
}
static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) {
check_dma_channel_param(channel);
check_hw_layout(dma_hw_t, inte1, DMA_INTE1_OFFSET);
if (enabled)
hw_set_bits(&dma_hw->inte1, 1u << channel);
else
hw_clear_bits(&dma_hw->inte1, 1u << channel);
}
static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
if (enabled) {
hw_set_bits(&dma_hw->inte1, channel_mask);
} else {
hw_clear_bits(&dma_hw->inte1, channel_mask);
}
}
static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
if (enabled)
hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel);
else
hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel);
}
static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
if (enabled) {
hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask);
} else {
hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask);
}
}
static inline bool dma_channel_get_irq0_status(uint channel) {
check_dma_channel_param(channel);
return dma_hw->ints0 & (1u << channel);
}
static inline bool dma_channel_get_irq1_status(uint channel) {
check_dma_channel_param(channel);
return dma_hw->ints1 & (1u << channel);
}
static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
check_dma_channel_param(channel);
return dma_hw->irq_ctrl[irq_index].ints & (1u << channel);
}
static inline void dma_channel_acknowledge_irq0(uint channel) {
check_dma_channel_param(channel);
dma_hw->ints0 = 1u << channel;
}
static inline void dma_channel_acknowledge_irq1(uint channel) {
check_dma_channel_param(channel);
dma_hw->ints1 = 1u << channel;
}
static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
check_dma_channel_param(channel);
dma_hw->irq_ctrl[irq_index].ints = 1u << channel;
}
inline static bool dma_channel_is_busy(uint channel) {
check_dma_channel_param(channel);
return dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS;
}
inline static void dma_channel_wait_for_finish_blocking(uint channel) {
while (dma_channel_is_busy(channel)) tight_loop_contents();
// stop the compiler hoisting a non-volatile buffer access above the DMA completion.
__compiler_memory_barrier();
}
inline static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable) {
check_dma_channel_param(channel);
check_hw_layout(dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET);
if (force_channel_enable) {
hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
}
hw_write_masked(&dma_hw->sniff_ctrl,
(((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) |
((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) |
DMA_SNIFF_CTRL_EN_BITS),
(DMA_SNIFF_CTRL_DMACH_BITS |
DMA_SNIFF_CTRL_CALC_BITS |
DMA_SNIFF_CTRL_EN_BITS));
}
inline static void dma_sniffer_set_byte_swap_enabled(bool swap) {
if (swap)
hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
else
hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
}
inline static void dma_sniffer_set_output_invert_enabled(bool invert) {
if (invert)
hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS);
else
hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS);
}
inline static void dma_sniffer_set_output_reverse_enabled(bool reverse) {
if (reverse)
hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS);
else
hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS);
}
inline static void dma_sniffer_disable(void) {
dma_hw->sniff_ctrl = 0;
}
inline static void dma_sniffer_set_data_accumulator(uint32_t seed_value) {
dma_hw->sniff_data = seed_value;
}
inline static uint32_t dma_sniffer_get_data_accumulator(void) {
return dma_hw->sniff_data;
}
void dma_timer_claim(uint timer);
void dma_timer_unclaim(uint timer);
int dma_claim_unused_timer(bool required);
bool dma_timer_is_claimed(uint timer);
static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) {
check_dma_timer_param(timer);
invalid_params_if(HARDWARE_DMA, numerator > denominator);
dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
}
static inline uint dma_get_timer_dreq(uint timer_num) {
static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, "");
static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, "");
static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, "");
check_dma_timer_param(timer_num);
return DREQ_DMA_TIMER0 + timer_num;
}
static inline int dma_get_irq_num(uint irq_index) {
valid_params_if(HARDWARE_DMA, irq_index < NUM_DMA_IRQS);
return DMA_IRQ_NUM(irq_index);
}
void dma_channel_cleanup(uint channel);
#ifndef NDEBUG
void print_dma_ctrl(dma_channel_hw_t *channel);
#endif
#ifdef __cplusplus
}
#endif
#endif
channel_config_set_enable
static void channel_config_set_enable(dma_channel_config_t *c, bool enable)
Enable/Disable the DMA channel in a channel configuration object.
Definition dma.h:393
channel_config_set_transfer_data_size
static void channel_config_set_transfer_data_size(dma_channel_config_t *c, dma_channel_transfer_size_t size)
Set the size of each DMA bus transfer in a channel configuration object.
Definition dma.h:310
channel_config_set_bswap
static void channel_config_set_bswap(dma_channel_config_t *c, bool bswap)
Set DMA byte swapping config in a channel configuration object.
Definition dma.h:346
channel_config_set_sniff_enable
static void channel_config_set_sniff_enable(dma_channel_config_t *c, bool sniff_enable)
Enable access to channel by sniff hardware in a channel configuration object.
Definition dma.h:405
channel_config_set_high_priority
static void channel_config_set_high_priority(dma_channel_config_t *c, bool high_priority)
Set the channel priority in a channel configuration object.
Definition dma.h:378
channel_config_set_read_increment
static void channel_config_set_read_increment(dma_channel_config_t *c, bool incr)
Set DMA channel read increment in a channel configuration object.
Definition dma.h:246
dma_channel_get_default_config
static dma_channel_config_t dma_channel_get_default_config(uint channel)
Get the default channel configuration for a given channel.
Definition dma.h:430
channel_config_set_read_address_update_type
static void channel_config_set_read_address_update_type(dma_channel_config_t *c, dma_address_update_type_t update_type)
Set DMA channel read address update type in a channel configuration object.
Definition dma.h:215
channel_config_set_write_address_update_type
static void channel_config_set_write_address_update_type(dma_channel_config_t *c, dma_address_update_type_t update_type)
Set DMA channel write address update type in a channel configuration object.
Definition dma.h:228
channel_config_set_write_increment
static void channel_config_set_write_increment(dma_channel_config_t *c, bool incr)
Set DMA channel write increment in a channel configuration object.
Definition dma.h:263
channel_config_get_ctrl_value
static uint32_t channel_config_get_ctrl_value(const dma_channel_config_t *config)
Get the raw configuration register from a channel configuration.
Definition dma.h:464
channel_config_set_dreq
static void channel_config_set_dreq(dma_channel_config_t *c, uint dreq)
Select a transfer request signal in a channel configuration object.
Definition dma.h:282
channel_config_set_chain_to
static void channel_config_set_chain_to(dma_channel_config_t *c, uint chain_to)
Set DMA channel chain_to channel in a channel configuration object.
Definition dma.h:296
channel_config_set_irq_quiet
static void channel_config_set_irq_quiet(dma_channel_config_t *c, bool irq_quiet)
Set IRQ quiet mode in a channel configuration object.
Definition dma.h:360
dma_get_channel_config
static dma_channel_config_t dma_get_channel_config(uint channel)
Get the current configuration for the specified channel.
Definition dma.h:452
channel_config_set_ring
static void channel_config_set_ring(dma_channel_config_t *c, bool write, uint size_bits)
Set address wrapping parameters in a channel configuration object.
Definition dma.h:330
hw_set_bits
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition address_mapped.h:135
hw_write_masked
static __force_inline void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask)
Set new values for a sub-set of the bits in a HW register.
Definition address_mapped.h:171
hw_clear_bits
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition address_mapped.h:145
dma_unclaim_mask
void dma_unclaim_mask(uint32_t channel_mask)
Mark multiple dma channels as no longer used.
Definition dma.c:39
dma_sniffer_enable
static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable)
Enable the DMA sniffing targeting the specified channel.
Definition dma.h:965
dma_timer_claim
void dma_timer_claim(uint timer)
Mark a dma timer as used.
Definition dma.c:54
dma_address_update_type
dma_address_update_type
Enumeration of types of updates that can be made to the DMA read or write address after each transfer...
Definition dma.h:152
dma_channel_set_transfer_count
static void dma_channel_set_transfer_count(uint channel, uint32_t encoded_transfer_count, bool trigger)
Set the number of bus transfers the channel will do.
Definition dma.h:605
dma_sniffer_set_output_invert_enabled
static void dma_sniffer_set_output_invert_enabled(bool invert)
Enable the Sniffer output invert function.
Definition dma.h:1006
dma_address_update_type_t
enum dma_address_update_type dma_address_update_type_t
Enumeration of types of updates that can be made to the DMA read or write address after each transfer...
dma_claim_unused_timer
int dma_claim_unused_timer(bool required)
Claim a free dma timer.
Definition dma.c:64
dma_sniffer_get_data_accumulator
static uint32_t dma_sniffer_get_data_accumulator(void)
Get the sniffer's data accumulator value.
Definition dma.h:1053
dma_channel_start
static void dma_channel_start(uint channel)
Start a single DMA channel.
Definition dma.h:714
dma_channel_set_config
static void dma_channel_set_config(uint channel, const dma_channel_config_t *config, bool trigger)
Set a channel configuration.
Definition dma.h:475
dma_irqn_get_channel_status
static bool dma_irqn_get_channel_status(uint irq_index, uint channel)
Determine if a particular channel is a cause of DMA_IRQ_N.
Definition dma.h:885
dma_claim_unused_channel
int dma_claim_unused_channel(bool required)
Claim a free dma channel.
Definition dma.c:45
dma_channel_acknowledge_irq1
static void dma_channel_acknowledge_irq1(uint channel)
Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1.
Definition dma.h:906
dma_channel_set_irq1_enabled
static void dma_channel_set_irq1_enabled(uint channel, bool enabled)
Enable single DMA channel's interrupt via DMA_IRQ_1.
Definition dma.h:801
dma_timer_set_fraction
static void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator)
Set the multiplier for the given DMA timer.
Definition dma.h:1105
dma_encode_transfer_count_with_self_trigger
static uint32_t dma_encode_transfer_count_with_self_trigger(uint transfer_count)
Encode the specified transfer length, along with a flag to indicate the DMA transfer should be self-t...
Definition dma.h:557
dma_get_irq_num
static int dma_get_irq_num(uint irq_index)
Return DMA_IRQ_<irqn>.
Definition dma.h:1130
dma_start_channel_mask
static void dma_start_channel_mask(uint32_t chan_mask)
Start one or more channels simultaneously.
Definition dma.h:704
dma_channel_cleanup
void dma_channel_cleanup(uint channel)
Performs DMA channel cleanup after use.
Definition dma.c:73
DMA_IRQ_NUM
#define DMA_IRQ_NUM(irq_index)
Returns the irq_num_t for the nth DMA interrupt.
Definition dma.h:56
dma_irqn_set_channel_enabled
static void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled)
Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1.
Definition dma.h:831
dma_irqn_set_channel_mask_enabled
static void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled)
Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1.
Definition dma.h:847
dma_channel_abort
static void dma_channel_abort(uint channel)
Stop a DMA transfer.
Definition dma.h:758
dma_get_timer_dreq
static uint dma_get_timer_dreq(uint timer_num)
Return the DREQ number for a given DMA timer.
Definition dma.h:1116
dma_timer_unclaim
void dma_timer_unclaim(uint timer)
Mark a dma timer as no longer used.
Definition dma.c:59
dma_encode_endless_transfer_count
static uint32_t dma_encode_endless_transfer_count(void)
Return an endless transfer as an "encoded_transfer_length" value suitable for the referenced methods.
Definition dma.h:577
dma_encode_transfer_count
static uint32_t dma_encode_transfer_count(uint transfer_count)
Encode the specified transfer length into an "encoded_transfer_length" value suitable for the referen...
Definition dma.h:531
dma_channel_is_claimed
bool dma_channel_is_claimed(uint channel)
Determine if a dma channel is claimed.
Definition dma.c:49
dma_timer_is_claimed
bool dma_timer_is_claimed(uint timer)
Determine if a dma timer is claimed.
Definition dma.c:68
dma_sniffer_disable
static void dma_sniffer_disable(void)
Disable the DMA sniffer.
Definition dma.h:1032
dma_sniffer_set_output_reverse_enabled
static void dma_sniffer_set_output_reverse_enabled(bool reverse)
Enable the Sniffer output bit reversal function.
Definition dma.h:1021
dma_claim_mask
void dma_claim_mask(uint32_t channel_mask)
Mark multiple dma channels as used.
Definition dma.c:28
dma_channel_get_irq0_status
static bool dma_channel_get_irq0_status(uint channel)
Determine if a particular channel is a cause of DMA_IRQ_0.
Definition dma.h:862
dma_set_irq1_channel_mask_enabled
static void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled)
Enable multiple DMA channels' interrupts via DMA_IRQ_1.
Definition dma.h:816
dma_channel_wait_for_finish_blocking
static void dma_channel_wait_for_finish_blocking(uint channel)
Wait for a DMA channel transfer to complete.
Definition dma.h:939
dma_channel_set_read_addr
static void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger)
Set the DMA initial read address.
Definition dma.h:491
dma_channel_transfer_to_buffer_now
static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t encoded_transfer_count)
Start a DMA transfer to a buffer immediately.
Definition dma.h:693
dma_sniffer_set_byte_swap_enabled
static void dma_sniffer_set_byte_swap_enabled(bool swap)
Enable the Sniffer byte swap function.
Definition dma.h:991
dma_channel_transfer_from_buffer_now
static void dma_channel_transfer_from_buffer_now(uint channel, const volatile void *read_addr, uint32_t encoded_transfer_count)
Start a DMA transfer from a buffer immediately.
Definition dma.h:666
dma_channel_unclaim
void dma_channel_unclaim(uint channel)
Mark a dma channel as no longer used.
Definition dma.c:34
dma_sniffer_set_data_accumulator
static void dma_sniffer_set_data_accumulator(uint32_t seed_value)
Set the sniffer's data accumulator with initial value.
Definition dma.h:1044
dma_channel_transfer_size
dma_channel_transfer_size
Enumeration of available DMA channel transfer sizes.
Definition dma.h:143
dma_irqn_acknowledge_channel
static void dma_irqn_acknowledge_channel(uint irq_index, uint channel)
Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N.
Definition dma.h:917
dma_set_irq0_channel_mask_enabled
static void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled)
Enable multiple DMA channels' interrupts via DMA_IRQ_0.
Definition dma.h:787
dma_channel_claim
void dma_channel_claim(uint channel)
Mark a dma channel as used.
Definition dma.c:23
dma_channel_transfer_size_t
enum dma_channel_transfer_size dma_channel_transfer_size_t
Enumeration of available DMA channel transfer sizes.
dma_channel_configure
static void dma_channel_configure(uint channel, const dma_channel_config_t *config, volatile void *write_addr, const volatile void *read_addr, uint32_t encoded_transfer_count, bool trigger)
Configure all DMA parameters and optionally start transfer.
Definition dma.h:639
dma_channel_set_write_addr
static void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger)
Set the DMA initial write address.
Definition dma.h:506
dma_channel_set_irq0_enabled
static void dma_channel_set_irq0_enabled(uint channel, bool enabled)
Enable single DMA channel's interrupt via DMA_IRQ_0.
Definition dma.h:772
dma_channel_get_irq1_status
static bool dma_channel_get_irq1_status(uint channel)
Determine if a particular channel is a cause of DMA_IRQ_1.
Definition dma.h:873
dma_channel_is_busy
static bool dma_channel_is_busy(uint channel)
Check if DMA channel is busy.
Definition dma.h:929
dma_channel_acknowledge_irq0
static void dma_channel_acknowledge_irq0(uint channel)
Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0.
Definition dma.h:896
DMA_ADDRESS_UPDATE_NONE
@ DMA_ADDRESS_UPDATE_NONE
The address remains the same after each transfer.
Definition dma.h:153
DMA_ADDRESS_UPDATE_INCREMENT
@ DMA_ADDRESS_UPDATE_INCREMENT
The address is incremented by the transfer size after each transfer.
Definition dma.h:154
DREQ_DMA_TIMER1
@ DREQ_DMA_TIMER1
Select DMA_TIMER0 as DREQ.
Definition dreq.h:108
DREQ_DMA_TIMER0
@ DREQ_DMA_TIMER0
Select DMA_TIMER0 as DREQ.
Definition dreq.h:107
DREQ_DMA_TIMER3
@ DREQ_DMA_TIMER3
Select DMA_TIMER3 as DREQ.
Definition dreq.h:110
DREQ_DMA_TIMER2
@ DREQ_DMA_TIMER2
Select DMA_TIMER1 as DREQ.
Definition dreq.h:109
DREQ_FORCE
@ DREQ_FORCE
Select FORCE as DREQ.
Definition dreq.h:111
DMA_SIZE_16
@ DMA_SIZE_16
Half word transfer (16 bits).
Definition dma.h:145
DMA_SIZE_8
@ DMA_SIZE_8
Byte transfer (8 bits).
Definition dma.h:144
DMA_SIZE_32
@ DMA_SIZE_32
Word transfer (32 bits).
Definition dma.h:146
panic_unsupported
void panic_unsupported(void)
Panics with the message "Unsupported".
Definition panic.c:20
tight_loop_contents
static __force_inline void tight_loop_contents(void)
No-op function for the body of tight loops.
Definition common.h:74
__compiler_memory_barrier
static __always_inline void __compiler_memory_barrier(void)
Ensure that the compiler does not move memory access across this method call.
Definition compiler.h:176
pico.h
dma_channel_config_t
Opaque representation of a DMA channel configuration that can be later applied to a hardware DMA chan...
Definition dma.h:164
dma_channel_hw_t
Definition dma.h:27
dma_hw_t
Definition dma.h:146