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v2.2.0 (RP2040)
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hardware_pll

Phase Locked Loop control APIs. More...

## Macros

#define | PLL_RESET_NUM(pll)
| Returns the reset_num_t used to reset a given PLL instance.

## Functions

void | pll_init (PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2)
| Initialise specified PLL.
void | pll_deinit (PLL pll)
| Release/uninitialise specified PLL.

## Detailed Description

Phase Locked Loop control APIs.

There are two PLLs in RP2040. They are:

- pll_sys - Used to generate up to a 133MHz system clock
- pll_usb - Used to generate a 48MHz USB reference clock

For details on how the PLLs are calculated, please refer to the RP2040 datasheet.

## Macro Definition Documentation

## PLL_RESET_NUM

#define PLL_RESET_NUM | ( |  | pll | ) |

Returns the reset_num_t used to reset a given PLL instance.

Note this macro is intended to resolve at compile time, and does no parameter checking

## Function Documentation

## pll_deinit()

void pll_deinit | ( | PLL | pll | ) |

Release/uninitialise specified PLL.

This will turn off the power to the specified PLL. Note this function does not currently check if the PLL is in use before powering it off so should be used with care.

Parameters

  pll | pll_sys or pll_usb

## pll_init()

void pll_init | ( | PLL | pll,
|  | uint | ref_div,
|  | uint | vco_freq,
|  | uint | post_div1,
|  | uint | post_div2 )

Initialise specified PLL.

Parameters

  pll | pll_sys or pll_usb
  ref_div | Input clock divider.
  vco_freq | Requested output from the VCO (voltage controlled oscillator)
  post_div1 | Post Divider 1 - range 1-7. Must be >= post_div2
  post_div2 | Post Divider 2 - range 1-7