## 14 PLD/FPGA Commands ¶

Programmable Logic Devices (PLDs) and the more flexible Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware. OpenOCD can support programming them. Although PLDs are generally restrictive (cells are less functional, and there are no special purpose cells for memory or computational tasks), they share the same OpenOCD infrastructure. Accordingly, both are called PLDs here.

### 14.1 PLD/FPGA Configuration and Commands ¶

As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND), OpenOCD maintains a list of PLDs available for use in various commands. Also, each such PLD requires a driver.

They are referenced by the number shown by the `pld devices` command, and new PLDs are defined by `pld device driver_name`.

Config Command: pld device driver_name tap_name [driver_options] ¶

  Defines a new PLD device, supported by driver driver_name, using the TAP named tap_name. The driver may make use of any driver_options to configure its behavior.

Command: pld devices ¶

  Lists the PLDs and their numbers.

Command: pld load num filename ¶

  Loads the file `filename` into the PLD identified by num. The file format must be inferred by the driver.

### 14.2 PLD/FPGA Drivers, Options, and Commands ¶

Drivers may support PLD-specific options to the `pld device` definition command, and may also define commands usable only with that particular type of PLD.

FPGA Driver: virtex2 [no_jstart] ¶

  Virtex-II is a family of FPGAs sold by Xilinx. This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices. It supports the IEEE 1532 standard for In-System Configuration (ISC).

  If no_jstart is non-zero, the JSTART instruction is not used after loading the bitstream. While required for Series2, Series3, and Series6, it breaks bitstream loading on Series7.

      openocd -f board/digilent_zedboard.cfg -c "init" \
      	-c "pld load 0 zedboard_bitstream.bit"

  Command: virtex2 read_stat num ¶

    Reads and displays the Virtex-II status register (STAT) for FPGA num.