reSIDfp::WaveformGenerator Class Reference

`#include <WaveformGenerator.h>`

## Public Member Functions

void | setWaveformModels (matrix_t *models)
void | setChipModel (ChipModel chipModel)
void | clock ()
void | synchronize (WaveformGenerator *syncDest, const WaveformGenerator *syncSource) const
| WaveformGenerator ()
void | writeFREQ_LO (unsigned char freq_lo)
void | writeFREQ_HI (unsigned char freq_hi)
void | writePW_LO (unsigned char pw_lo)
void | writePW_HI (unsigned char pw_hi)
void | writeCONTROL_REG (unsigned char control)
void | reset ()
short | output (const WaveformGenerator *ringModulator)
unsigned char | readOSC () const
int | readAccumulator () const
int | readFreq () const
bool | readTest () const
bool | readSync () const

## Detailed Description

A 24 bit accumulator is the basis for waveform generation. FREQ is added to the lower 16 bits of the accumulator each cycle. The accumulator is set to zero when TEST is set, and starts counting when TEST is cleared.

Waveforms are generated as follows:

- No waveform: When no waveform is selected, the DAC input is floating.
- Triangle: The upper 12 bits of the accumulator are used. The MSB is used to create the falling edge of the triangle by inverting the lower 11 bits. The MSB is thrown away and the lower 11 bits are left-shifted (half the resolution, full amplitude). Ring modulation substitutes the MSB with MSB EOR sync_source MSB.
- Sawtooth: The output is identical to the upper 12 bits of the accumulator.
- Pulse: The upper 12 bits of the accumulator are used. These bits are compared to the pulse width register by a 12 bit digital comparator; output is either all one or all zero bits. The pulse setting is delayed one cycle after the compare; this is only modeled for single cycle clocking. The test bit, when set to one, holds the pulse waveform output at 0xfff regardless of the pulse width setting.
- Noise: The noise output is taken from intermediate bits of a 23-bit shift register which is clocked by bit 19 of the accumulator. The shift is delayed 2 cycles after bit 19 is set high; this is only modeled for single cycle clocking.

Operation: Calculate EOR result, shift register, set bit 0 = result.

                   reset    -------------------------------------------
                     |     |                                           |
              test--OR-->EOR<--                                        |
                     |         |                                       |
                     2 2 2 1 1 1 1 1 1 1 1 1 1                         |
    Register bits:   2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <---
                         |   |       |     |   |       |     |   |
    Waveform bits:       1   1       9     8   7       6     5   4
                         1   0

The low 4 waveform bits are zero (grounded).

## Constructor & Destructor Documentation

reSIDfp::WaveformGenerator::WaveformGenerator | ( |  | ) |

inline

Constructor.

## Member Function Documentation

RESID_INLINE void reSIDfp::WaveformGenerator::clock | ( |  | ) |

SID clocking - 1 cycle.

RESID_INLINE short reSIDfp::WaveformGenerator::output | ( | const WaveformGenerator * | ringModulator | ) |

12-bit waveform output. The output from SID 8580 is delayed one cycle compared to SID 6581;

Parameters

  ringModulator | The oscillator ring-modulating me.

Returns
  output from waveform generator

int reSIDfp::WaveformGenerator::readAccumulator | ( |  | ) | const

inline

Read accumulator value.

int reSIDfp::WaveformGenerator::readFreq | ( |  | ) | const

inline

Read freq value.

unsigned char reSIDfp::WaveformGenerator::readOSC | ( |  | ) | const

inline

Read OSC3 value (6581, not latched/delayed version)

bool reSIDfp::WaveformGenerator::readSync | ( |  | ) | const

inline

Read sync value.

bool reSIDfp::WaveformGenerator::readTest | ( |  | ) | const

inline

Read test value.

void reSIDfp::WaveformGenerator::reset | ( |  | ) |

SID reset.

void reSIDfp::WaveformGenerator::setChipModel | ( | ChipModel | chipModel | ) |

Set the chip model. This determines the type of the analog DAC emulation: 8580 is perfectly linear while 6581 is nonlinear.

Parameters

  chipModel |

void reSIDfp::WaveformGenerator::synchronize | ( | WaveformGenerator * | syncDest,
|  | const WaveformGenerator * | syncSource
| ) |  | const

Synchronize oscillators. This must be done after all the oscillators have been clock()'ed, so that they are in the same state.

Parameters

  syncDest | The oscillator I am syncing
  syncSource | The oscillator syncing me.

void reSIDfp::WaveformGenerator::writeCONTROL_REG | ( | unsigned char | control | ) |

Register functions.

Parameters

  control | control register value

void reSIDfp::WaveformGenerator::writeFREQ_HI | ( | unsigned char | freq_hi | ) |

inline

Register functions.

Parameters

  freq_hi | high 8 bits of frequency

void reSIDfp::WaveformGenerator::writeFREQ_LO | ( | unsigned char | freq_lo | ) |

inline

Register functions.

Parameters

  freq_lo | low 8 bits of frequency

void reSIDfp::WaveformGenerator::writePW_HI | ( | unsigned char | pw_hi | ) |

inline

Register functions.

Parameters

  pw_hi | high 8 bits of pulse width

void reSIDfp::WaveformGenerator::writePW_LO | ( | unsigned char | pw_lo | ) |

inline

Register functions.

The original form was (acc >> 12) >= pw, where truth value is not affected by the contents of the low 12 bits. Therefore the lowest bits must be zero in the new formulation acc >= (pw << 12).

Parameters

  pw_lo | low 8 bits of pulse width

The documentation for this class was generated from the following files:

- WaveformGenerator.h
- WaveformGenerator.cpp