trc_cmp_cfg_etmv3.h
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/*
* \file trc_cmp_cfg_etmv3.h
* \brief OpenCSD :
*
* \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
*/
/*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED
#define ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED
#include "trc_pkt_types_etmv3.h"
#include "common/trc_cs_config.h"
class EtmV3Config : public CSConfig
{
public:
EtmV3Config();
EtmV3Config(const ocsd_etmv3_cfg *cfg_regs);
~EtmV3Config() {};
/* register bit constants. */
static const uint32_t CTRL_DATAVAL = 0x4;
static const uint32_t CTRL_DATAADDR = 0x8;
static const uint32_t CTRL_CYCLEACC = 0x1000;
static const uint32_t CTRL_DATAONLY = 0x100000;
static const uint32_t CTRL_TS_ENA = (0x1 << 28);
static const uint32_t CTRL_VMID_ENA = (0x1 << 30);
static const uint32_t CCER_HAS_TS = (0x1 << 22);
static const uint32_t CCER_VIRTEXT = (0x1 << 26);
static const uint32_t CCER_TS64BIT = (0x1 << 29);
static const uint32_t IDR_ALTBRANCH = 0x100000;
// operations to convert to and from C-API structure
EtmV3Config & operator=(const ocsd_etmv3_cfg *p_cfg);
operator const ocsd_etmv3_cfg &() const { return m_cfg; };
operator const ocsd_etmv3_cfg *() const { return &m_cfg; };
enum EtmTraceMode {
TM_INSTR_ONLY,
TM_I_DATA_VAL,
TM_I_DATA_ADDR,
TM_I_DATA_VAL_ADDR,
TM_DATAONLY_VAL,
TM_DATAONLY_ADDR,
TM_DATAONLY_VAL_ADDR
};
EtmTraceMode const GetTraceMode() const;
const bool isInstrTrace() const;
const bool isDataValTrace() const;
const bool isDataAddrTrace() const;
const bool isDataTrace() const;
const bool isCycleAcc() const;
const int MinorRev() const;
const bool isV7MArch() const;
const bool isAltBranch() const;
const int CtxtIDBytes() const;
const bool hasVirtExt() const;
const bool isVMIDTrace() const;
const bool hasTS() const;
const bool isTSEnabled() const;
const bool TSPkt64() const;
virtual const uint8_t getTraceID() const;
const ocsd_arch_version_t getArchVersion() const;
const ocsd_core_profile_t getCoreProfile() const;
private:
ocsd_etmv3_cfg m_cfg;
};
/* inlines for the bit interpretations */
inline EtmV3Config & EtmV3Config::operator=(const ocsd_etmv3_cfg *p_cfg)
{
m_cfg = *p_cfg;
return *this;
}
inline const bool EtmV3Config::isCycleAcc() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0);
}
inline const int EtmV3Config::MinorRev() const
{
return ((int)m_cfg.reg_idr & 0xF0) >> 4;
}
inline const bool EtmV3Config::isInstrTrace() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_DATAONLY) == 0);
}
inline const bool EtmV3Config::isDataValTrace() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_DATAVAL) != 0);
}
inline const bool EtmV3Config::isDataAddrTrace() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_DATAADDR) != 0);
}
inline const bool EtmV3Config::isDataTrace() const
{
return (bool)((m_cfg.reg_ctrl & (CTRL_DATAADDR | CTRL_DATAVAL)) != 0);
}
inline const bool EtmV3Config::isV7MArch() const
{
return (bool)((m_cfg.arch_ver == ARCH_V7) && (m_cfg.core_prof == profile_CortexM));
}
inline const bool EtmV3Config::isAltBranch() const
{
return (bool)(((m_cfg.reg_idr & IDR_ALTBRANCH) != 0) && (MinorRev() >= 4));
}
inline const bool EtmV3Config::hasVirtExt() const
{
return (bool)((m_cfg.reg_ccer & CCER_VIRTEXT) != 0);
}
inline const bool EtmV3Config::TSPkt64() const
{
return (bool)((m_cfg.reg_ccer & CCER_TS64BIT) != 0);
}
inline const bool EtmV3Config::hasTS() const
{
return (bool)((m_cfg.reg_ccer & CCER_HAS_TS) != 0);
}
inline const bool EtmV3Config::isTSEnabled() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0);
}
inline const bool EtmV3Config::isVMIDTrace() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0);
}
inline const uint8_t EtmV3Config::getTraceID() const
{
return (uint8_t)(m_cfg.reg_trc_id & 0x7F);
}
inline const ocsd_arch_version_t EtmV3Config::getArchVersion() const
{
return m_cfg.arch_ver;
}
inline const ocsd_core_profile_t EtmV3Config::getCoreProfile() const
{
return m_cfg.core_prof;
}
#endif // ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED
/* End of File trc_cmp_cfg_etmv3.h */
CSConfig
Base class for configuration data on CoreSight trace component.
Definition: trc_cs_config.h:50
EtmV3Config
Interpreter class for etm v3 config structure.
Definition: trc_cmp_cfg_etmv3.h:59
EtmV3Config::EtmV3Config
EtmV3Config(const ocsd_etmv3_cfg *cfg_regs)
EtmV3Config::EtmV3Config
EtmV3Config()
EtmV3Config::~EtmV3Config
~EtmV3Config()
Definition: trc_cmp_cfg_etmv3.h:63
EtmV3Config::CCER_HAS_TS
static const uint32_t CCER_HAS_TS
Definition: trc_cmp_cfg_etmv3.h:73
EtmV3Config::CTRL_VMID_ENA
static const uint32_t CTRL_VMID_ENA
Definition: trc_cmp_cfg_etmv3.h:71
EtmV3Config::GetTraceMode
EtmTraceMode const GetTraceMode() const
return trace mode
EtmV3Config::CCER_VIRTEXT
static const uint32_t CCER_VIRTEXT
Definition: trc_cmp_cfg_etmv3.h:74
EtmV3Config::CTRL_DATAONLY
static const uint32_t CTRL_DATAONLY
Definition: trc_cmp_cfg_etmv3.h:69
EtmV3Config::CTRL_CYCLEACC
static const uint32_t CTRL_CYCLEACC
Definition: trc_cmp_cfg_etmv3.h:68
EtmV3Config::CCER_TS64BIT
static const uint32_t CCER_TS64BIT
Definition: trc_cmp_cfg_etmv3.h:75
EtmV3Config::CtxtIDBytes
const int CtxtIDBytes() const
number of context ID bytes traced 1,2,4;
EtmV3Config::CTRL_DATAADDR
static const uint32_t CTRL_DATAADDR
Definition: trc_cmp_cfg_etmv3.h:67
EtmV3Config::CTRL_TS_ENA
static const uint32_t CTRL_TS_ENA
Definition: trc_cmp_cfg_etmv3.h:70
EtmV3Config::CTRL_DATAVAL
static const uint32_t CTRL_DATAVAL
Definition: trc_cmp_cfg_etmv3.h:66
EtmV3Config::IDR_ALTBRANCH
static const uint32_t IDR_ALTBRANCH
Definition: trc_cmp_cfg_etmv3.h:77
EtmV3Config::EtmTraceMode
EtmTraceMode
combination enum to describe trace mode.
Definition: trc_cmp_cfg_etmv3.h:90
EtmV3Config::TM_I_DATA_ADDR
@ TM_I_DATA_ADDR
instruction + data address
Definition: trc_cmp_cfg_etmv3.h:93
EtmV3Config::TM_DATAONLY_VAL_ADDR
@ TM_DATAONLY_VAL_ADDR
data value + address trace
Definition: trc_cmp_cfg_etmv3.h:97
EtmV3Config::TM_DATAONLY_VAL
@ TM_DATAONLY_VAL
data value trace
Definition: trc_cmp_cfg_etmv3.h:95
EtmV3Config::TM_INSTR_ONLY
@ TM_INSTR_ONLY
instruction only trace
Definition: trc_cmp_cfg_etmv3.h:91
EtmV3Config::TM_I_DATA_VAL_ADDR
@ TM_I_DATA_VAL_ADDR
instr + data value + data address
Definition: trc_cmp_cfg_etmv3.h:94
EtmV3Config::TM_I_DATA_VAL
@ TM_I_DATA_VAL
instruction + data value
Definition: trc_cmp_cfg_etmv3.h:92
EtmV3Config::TM_DATAONLY_ADDR
@ TM_DATAONLY_ADDR
data address trace
Definition: trc_cmp_cfg_etmv3.h:96
ocsd_core_profile_t
enum _ocsd_core_profile ocsd_core_profile_t
ocsd_arch_version_t
enum _ocsd_arch_version ocsd_arch_version_t
profile_CortexM
@ profile_CortexM
Definition: ocsd_if_types.h:292
ARCH_V7
@ ARCH_V7
Definition: ocsd_if_types.h:278
EtmV3Config::hasVirtExt
const bool hasVirtExt() const
processor has virtualisation extensions.
Definition: trc_cmp_cfg_etmv3.h:185
EtmV3Config::isTSEnabled
const bool isTSEnabled() const
Timestamp trace is enabled.
Definition: trc_cmp_cfg_etmv3.h:203
EtmV3Config::isV7MArch
const bool isV7MArch() const
source is V7M architecture
Definition: trc_cmp_cfg_etmv3.h:173
EtmV3Config::TSPkt64
const bool TSPkt64() const
timestamp packet is 64 bits in size.
Definition: trc_cmp_cfg_etmv3.h:191
EtmV3Config::isDataValTrace
const bool isDataValTrace() const
data value trace present.
Definition: trc_cmp_cfg_etmv3.h:157
EtmV3Config::MinorRev
const int MinorRev() const
return X revision in 3.X
Definition: trc_cmp_cfg_etmv3.h:147
EtmV3Config::getTraceID
virtual const uint8_t getTraceID() const
CoreSight Trace ID for this device.
Definition: trc_cmp_cfg_etmv3.h:214
EtmV3Config::hasTS
const bool hasTS() const
Timestamps implemented in trace.
Definition: trc_cmp_cfg_etmv3.h:197
EtmV3Config::getArchVersion
const ocsd_arch_version_t getArchVersion() const
architecture version
Definition: trc_cmp_cfg_etmv3.h:219
EtmV3Config::isVMIDTrace
const bool isVMIDTrace() const
VMID tracing enabled.
Definition: trc_cmp_cfg_etmv3.h:209
EtmV3Config::isCycleAcc
const bool isCycleAcc() const
return true if cycle accurate tracing enabled.
Definition: trc_cmp_cfg_etmv3.h:141
EtmV3Config::isAltBranch
const bool isAltBranch() const
Alternate branch packet encoding used.
Definition: trc_cmp_cfg_etmv3.h:179
EtmV3Config::isDataTrace
const bool isDataTrace() const
either or both data trace types present.
Definition: trc_cmp_cfg_etmv3.h:168
EtmV3Config::operator=
EtmV3Config & operator=(const ocsd_etmv3_cfg *p_cfg)
copy assignment operator for C-API base structure into class.
Definition: trc_cmp_cfg_etmv3.h:135
EtmV3Config::isInstrTrace
const bool isInstrTrace() const
instruction trace present.
Definition: trc_cmp_cfg_etmv3.h:152
EtmV3Config::getCoreProfile
const ocsd_core_profile_t getCoreProfile() const
core profile.
Definition: trc_cmp_cfg_etmv3.h:224
EtmV3Config::isDataAddrTrace
const bool isDataAddrTrace() const
data address trace present.
Definition: trc_cmp_cfg_etmv3.h:162
_ocsd_etmv3_cfg
Definition: trc_pkt_types_etmv3.h:162
_ocsd_etmv3_cfg::reg_ccer
uint32_t reg_ccer
Definition: trc_pkt_types_etmv3.h:165
_ocsd_etmv3_cfg::reg_ctrl
uint32_t reg_ctrl
Definition: trc_pkt_types_etmv3.h:164
_ocsd_etmv3_cfg::core_prof
ocsd_core_profile_t core_prof
Definition: trc_pkt_types_etmv3.h:168
_ocsd_etmv3_cfg::reg_trc_id
uint32_t reg_trc_id
Definition: trc_pkt_types_etmv3.h:166
_ocsd_etmv3_cfg::reg_idr
uint32_t reg_idr
Definition: trc_pkt_types_etmv3.h:163
_ocsd_etmv3_cfg::arch_ver
ocsd_arch_version_t arch_ver
Definition: trc_pkt_types_etmv3.h:167
trc_cs_config.h
trc_pkt_types_etmv3.h