trc_cmp_cfg_ptm.h
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/*
* \file trc_cmp_cfg_ptm.h
* \brief OpenCSD :
*
* \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
*/
/*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ARM_TRC_CMP_CFG_PTM_H_INCLUDED
#define ARM_TRC_CMP_CFG_PTM_H_INCLUDED
#include "trc_pkt_types_ptm.h"
#include "common/trc_cs_config.h"
class PtmConfig : public CSConfig // public ocsd_ptm_cfg
{
public:
PtmConfig();
PtmConfig(const ocsd_ptm_cfg *cfg_regs);
~PtmConfig() {};
/* register bit constants. */
static const uint32_t CTRL_BRANCH_BCAST = (0x1 << 8);
static const uint32_t CTRL_CYCLEACC = (0x1 << 12);
static const uint32_t CTRL_TS_ENA = (0x1 << 28);
static const uint32_t CTRL_RETSTACK_ENA = (0x1 << 29);
static const uint32_t CTRL_VMID_ENA = (0x1 << 30);
static const uint32_t CCER_TS_IMPL = (0x1 << 22);
static const uint32_t CCER_RESTACK_IMPL = (0x1 << 23);
static const uint32_t CCER_DMSB_WPT = (0x1 << 24);
static const uint32_t CCER_TS_DMSB = (0x1 << 25);
static const uint32_t CCER_VIRTEXT = (0x1 << 26);
static const uint32_t CCER_TS_ENC_NAT = (0x1 << 28);
static const uint32_t CCER_TS_64BIT = (0x1 << 29);
// operations to convert to and from C-API structure
PtmConfig & operator=(const ocsd_ptm_cfg *p_cfg);
operator const ocsd_ptm_cfg &() const { return m_cfg; };
operator const ocsd_ptm_cfg *() const { return &m_cfg; };
// access functions
const bool enaBranchBCast() const;
const bool enaCycleAcc() const;
const bool enaRetStack() const;
const bool hasRetStack() const;
const int MinorRev() const;
const bool hasTS() const;
const bool enaTS() const;
const bool TSPkt64() const;
const bool TSBinEnc() const;
const int CtxtIDBytes() const;
const bool hasVirtExt() const;
const bool enaVMID() const;
const bool dmsbGenTS() const;
const bool dmsbWayPt() const;
virtual const uint8_t getTraceID() const;
const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; };
const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; };
private:
ocsd_ptm_cfg m_cfg;
};
/* inlines */
inline PtmConfig & PtmConfig::operator=(const ocsd_ptm_cfg *p_cfg)
{
// object of base class ocsd_ptm_cfg
m_cfg = *p_cfg;
return *this;
}
inline const bool PtmConfig::enaBranchBCast() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_BRANCH_BCAST) != 0);
}
inline const bool PtmConfig::enaCycleAcc() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0);
}
inline const bool PtmConfig::enaRetStack() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_RETSTACK_ENA) != 0);
}
inline const bool PtmConfig::hasRetStack() const
{
return (bool)((m_cfg.reg_ccer & CCER_RESTACK_IMPL) != 0);
}
inline const int PtmConfig::MinorRev() const
{
return ((int)m_cfg.reg_idr & 0xF0) >> 4;
}
inline const bool PtmConfig::hasTS() const
{
return (bool)((m_cfg.reg_ccer & CCER_TS_IMPL) != 0);
}
inline const bool PtmConfig::enaTS() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0);
}
inline const bool PtmConfig::TSPkt64() const
{
if(MinorRev() == 0) return false;
return (bool)((m_cfg.reg_ccer & CCER_TS_64BIT) != 0);
}
inline const bool PtmConfig::TSBinEnc() const
{
if(MinorRev() == 0) return false;
return (bool)((m_cfg.reg_ccer & CCER_TS_ENC_NAT) != 0);
}
inline const bool PtmConfig::hasVirtExt() const
{
return (bool)((m_cfg.reg_ccer & CCER_VIRTEXT) != 0);
}
inline const bool PtmConfig::enaVMID() const
{
return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0);
}
inline const bool PtmConfig::dmsbGenTS() const
{
return (bool)((m_cfg.reg_ccer & CCER_TS_DMSB) != 0);
}
inline const bool PtmConfig::dmsbWayPt() const
{
return (bool)((m_cfg.reg_ccer & CCER_DMSB_WPT) != 0);
}
inline const uint8_t PtmConfig::getTraceID() const
{
return (uint8_t)(m_cfg.reg_trc_id & 0x7F);
}
#endif // ARM_TRC_CMP_CFG_PTM_H_INCLUDED
/* End of File trc_cmp_cfg_ptm.h */
PtmConfig::hasTS
const bool hasTS() const
Timestamps implemented in trace.
Definition: trc_cmp_cfg_ptm.h:159
trc_cs_config.h
PtmConfig::MinorRev
const int MinorRev() const
return X revision in 1.X
Definition: trc_cmp_cfg_ptm.h:154
CSConfig
Base class for configuration data on CoreSight trace component.
Definition: trc_cs_config.h:49
PtmConfig::TSPkt64
const bool TSPkt64() const
timestamp packet is 64 bits in size.
Definition: trc_cmp_cfg_ptm.h:169
ocsd_arch_version_t
enum _ocsd_arch_version ocsd_arch_version_t
PtmConfig::PtmConfig
PtmConfig()
PtmConfig::CTRL_CYCLEACC
static const uint32_t CTRL_CYCLEACC
Definition: trc_cmp_cfg_ptm.h:71
PtmConfig::archVersion
const ocsd_arch_version_t & archVersion() const
Definition: trc_cmp_cfg_ptm.h:119
PtmConfig::enaVMID
const bool enaVMID() const
VMID tracing enabled.
Definition: trc_cmp_cfg_ptm.h:186
_ocsd_ptm_cfg::reg_ctrl
uint32_t reg_ctrl
Definition: trc_pkt_types_ptm.h:124
PtmConfig::operator=
PtmConfig & operator=(const ocsd_ptm_cfg *p_cfg)
copy assignment operator for base structure into class.
Definition: trc_cmp_cfg_ptm.h:127
PtmConfig::CTRL_VMID_ENA
static const uint32_t CTRL_VMID_ENA
Definition: trc_cmp_cfg_ptm.h:74
PtmConfig::enaRetStack
const bool enaRetStack() const
return stack enabled.
Definition: trc_cmp_cfg_ptm.h:144
_ocsd_ptm_cfg
Definition: trc_pkt_types_ptm.h:121
_ocsd_ptm_cfg::arch_ver
ocsd_arch_version_t arch_ver
Definition: trc_pkt_types_ptm.h:127
PtmConfig::CCER_TS_64BIT
static const uint32_t CCER_TS_64BIT
Definition: trc_cmp_cfg_ptm.h:82
PtmConfig::coreProfile
const ocsd_core_profile_t & coreProfile() const
Definition: trc_cmp_cfg_ptm.h:118
PtmConfig::CCER_TS_IMPL
static const uint32_t CCER_TS_IMPL
Definition: trc_cmp_cfg_ptm.h:76
PtmConfig::enaTS
const bool enaTS() const
Timestamp trace is enabled.
Definition: trc_cmp_cfg_ptm.h:164
_ocsd_ptm_cfg::reg_ccer
uint32_t reg_ccer
Definition: trc_pkt_types_ptm.h:125
PtmConfig::CCER_DMSB_WPT
static const uint32_t CCER_DMSB_WPT
Definition: trc_cmp_cfg_ptm.h:78
PtmConfig::CCER_VIRTEXT
static const uint32_t CCER_VIRTEXT
Definition: trc_cmp_cfg_ptm.h:80
PtmConfig::enaBranchBCast
const bool enaBranchBCast() const
Branch broadcast enabled.
Definition: trc_cmp_cfg_ptm.h:134
PtmConfig::dmsbWayPt
const bool dmsbWayPt() const
DMB and DSB are waypoint instructions.
Definition: trc_cmp_cfg_ptm.h:196
PtmConfig::CCER_TS_ENC_NAT
static const uint32_t CCER_TS_ENC_NAT
Definition: trc_cmp_cfg_ptm.h:81
PtmConfig::CCER_RESTACK_IMPL
static const uint32_t CCER_RESTACK_IMPL
Definition: trc_cmp_cfg_ptm.h:77
PtmConfig::hasRetStack
const bool hasRetStack() const
return stack implemented.
Definition: trc_cmp_cfg_ptm.h:149
trc_pkt_types_ptm.h
_ocsd_ptm_cfg::reg_idr
uint32_t reg_idr
Definition: trc_pkt_types_ptm.h:123
PtmConfig::getTraceID
virtual const uint8_t getTraceID() const
CoreSight Trace ID for this device.
Definition: trc_cmp_cfg_ptm.h:201
PtmConfig
Interpreter class for PTM Hardware configuration.
Definition: trc_cmp_cfg_ptm.h:62
_ocsd_ptm_cfg::reg_trc_id
uint32_t reg_trc_id
Definition: trc_pkt_types_ptm.h:126
PtmConfig::TSBinEnc
const bool TSBinEnc() const
Timestamp encoded as natural binary number.
Definition: trc_cmp_cfg_ptm.h:175
PtmConfig::dmsbGenTS
const bool dmsbGenTS() const
TS generated for DMB and DSB.
Definition: trc_cmp_cfg_ptm.h:191
PtmConfig::CTRL_TS_ENA
static const uint32_t CTRL_TS_ENA
Definition: trc_cmp_cfg_ptm.h:72
PtmConfig::CTRL_RETSTACK_ENA
static const uint32_t CTRL_RETSTACK_ENA
Definition: trc_cmp_cfg_ptm.h:73
_ocsd_ptm_cfg::core_prof
ocsd_core_profile_t core_prof
Definition: trc_pkt_types_ptm.h:128
PtmConfig::~PtmConfig
~PtmConfig()
Definition: trc_cmp_cfg_ptm.h:67
PtmConfig::hasVirtExt
const bool hasVirtExt() const
processor has virtualisation extensions.
Definition: trc_cmp_cfg_ptm.h:181
ocsd_core_profile_t
enum _ocsd_core_profile ocsd_core_profile_t
PtmConfig::enaCycleAcc
const bool enaCycleAcc() const
cycle accurate tracing enabled.
Definition: trc_cmp_cfg_ptm.h:139
PtmConfig::CTRL_BRANCH_BCAST
static const uint32_t CTRL_BRANCH_BCAST
Definition: trc_cmp_cfg_ptm.h:70
PtmConfig::CCER_TS_DMSB
static const uint32_t CCER_TS_DMSB
Definition: trc_cmp_cfg_ptm.h:79
PtmConfig::CtxtIDBytes
const int CtxtIDBytes() const
number of context ID bytes traced 1,2,4;