trc_mem_acc_cache.h
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#ifndef ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
#define ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
#include <string>
#include "opencsd/ocsd_if_types.h"
#define MEM_ACC_CACHE_PAGE_SIZE 256
#define MEM_ACC_CACHE_MRU_SIZE 12
class TrcMemAccessorBase;
class ITraceErrorLog;
typedef struct cache_block {
ocsd_vaddr_t st_addr;
uint32_t valid_len;
uint8_t data[MEM_ACC_CACHE_PAGE_SIZE];
} cache_block_t;
// enable define to collect stats for debugging / cache performance tests
//#define LOG_CACHE_STATS
class TrcMemAccCache
{
public:
TrcMemAccCache();
~TrcMemAccCache() {};
void enableCaching(bool bEnable) { m_bCacheEnabled = bEnable; };
void invalidateAll();
const bool enabled() const { return m_bCacheEnabled; };
const bool enabled_for_size(const uint32_t reqSize) const
{
return (m_bCacheEnabled && (reqSize <= MEM_ACC_CACHE_PAGE_SIZE));
}
ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer);
void setErrorLog(ITraceErrorLog *log);
void logAndClearCounts();
private:
bool blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes); // run through each page to look for data.
bool blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes);
void logMsg(const std::string &szMsg);
cache_block_t m_mru[MEM_ACC_CACHE_MRU_SIZE];
int m_mru_idx = 0; // in use index
int m_mru_next_new = 0; // next new page at this index.
bool m_bCacheEnabled = false;
#ifdef LOG_CACHE_STATS
uint32_t m_hits = 0;
uint32_t m_misses = 0;
uint32_t m_pages = 0;
uint32_t m_hit_rl[MEM_ACC_CACHE_MRU_SIZE];
uint32_t m_hit_rl_max[MEM_ACC_CACHE_MRU_SIZE];
#endif
ITraceErrorLog *m_err_log = 0;
};
inline TrcMemAccCache::TrcMemAccCache()
{
for (int i = 0; i < MEM_ACC_CACHE_MRU_SIZE; i++)
{
m_mru[i].st_addr = 0;
m_mru[i].valid_len = 0;
#ifdef LOG_CACHE_STATS
m_hit_rl[i] = 0;
m_hit_rl_max[i] = 0;
#endif
}
}
inline bool TrcMemAccCache::blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes)
{
if ((m_mru[m_mru_idx].st_addr <= address) &&
m_mru[m_mru_idx].st_addr + m_mru[m_mru_idx].valid_len >= (address + reqBytes))
return true;
return false;
}
inline bool TrcMemAccCache::blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes)
{
int tests = MEM_ACC_CACHE_MRU_SIZE;
while (tests)
{
if (blockInPage(address, reqBytes))
return true; // found address in page
tests--;
m_mru_idx++;
if (m_mru_idx == MEM_ACC_CACHE_MRU_SIZE)
m_mru_idx = 0;
}
return false;
}
inline void TrcMemAccCache::invalidateAll()
{
for (int i = 0; i < MEM_ACC_CACHE_MRU_SIZE; i++)
{
m_mru[i].valid_len = 0;
m_mru[i].st_addr = 0;
}
m_mru_idx = 0;
m_mru_next_new = 0;
}
#endif // ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
/* End of File trc_mem_acc_cache.h */
ocsd_err_t
enum _ocsd_err_t ocsd_err_t
ITraceErrorLog
Error logging interface.
Definition: trc_error_log_i.h:56
cache_block::data
uint8_t data[MEM_ACC_CACHE_PAGE_SIZE]
Definition: trc_mem_acc_cache.h:50
TrcMemAccCache::enableCaching
void enableCaching(bool bEnable)
Definition: trc_mem_acc_cache.h:64
TrcMemAccessorBase
Memory range to access by trace decoder.
Definition: trc_mem_acc_base.h:52
TrcMemAccCache::enabled
const bool enabled() const
Definition: trc_mem_acc_cache.h:66
TrcMemAccCache
Definition: trc_mem_acc_cache.h:58
ocsd_if_types.h
OpenCSD : Standard Types used in the library interfaces.
ocsd_vaddr_t
uint64_t ocsd_vaddr_t
Definition: ocsd_if_types.h:308
TrcMemAccCache::enabled_for_size
const bool enabled_for_size(const uint32_t reqSize) const
Definition: trc_mem_acc_cache.h:67
cache_block
Definition: trc_mem_acc_cache.h:47
cache_block::valid_len
uint32_t valid_len
Definition: trc_mem_acc_cache.h:49
TrcMemAccCache::~TrcMemAccCache
~TrcMemAccCache()
Definition: trc_mem_acc_cache.h:62
TrcMemAccCache::logAndClearCounts
void logAndClearCounts()
TrcMemAccCache::setErrorLog
void setErrorLog(ITraceErrorLog *log)
TrcMemAccCache::TrcMemAccCache
TrcMemAccCache()
Definition: trc_mem_acc_cache.h:100
MEM_ACC_CACHE_PAGE_SIZE
#define MEM_ACC_CACHE_PAGE_SIZE
Definition: trc_mem_acc_cache.h:41
TrcMemAccCache::readBytesFromCache
ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer)
cache_block::st_addr
ocsd_vaddr_t st_addr
Definition: trc_mem_acc_cache.h:48
cache_block_t
struct cache_block cache_block_t
ocsd_mem_space_acc_t
enum _ocsd_mem_space_acc_t ocsd_mem_space_acc_t
TrcMemAccCache::invalidateAll
void invalidateAll()
Definition: trc_mem_acc_cache.h:136
MEM_ACC_CACHE_MRU_SIZE
#define MEM_ACC_CACHE_MRU_SIZE
Definition: trc_mem_acc_cache.h:42