# The Icarus Verilog Targets

Icarus Verilog elaborates the design, then sends to the design to code generates (targets) for processing. New code generators can be added by external packages, but these are the code generators that are bundled with Icarus Verilog. The code generator is selected by the “-t” command line flag.

- The vvp Code Generator (-tvvp)
- The stub Code Generator (-tstub)
- The null Code Generator (-tnull)
- The VHDL Code Generator (-tvhdl)
- The Verilog ‘95 Code Generator (-tvlog95)
- The PCB Code Generator (-tpcb)
- The FPGA Code Generator (-tfpga)
- The PAL Code Generator (-tpal)
- The sizer Code Analyzer (-tsizer)
- The Verilog Code Generator (-tverilog)
- The BLIF Code Generator (-tblif)