clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

Copyright | (C) 2023 QBayLogic B.V.
License | BSD2 (see the file LICENSE)
Maintainer | QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell | None
Language | Haskell2010

Clash.Explicit.BlockRam.Model

Description

Configurable model for true dual-port block RAM

Synopsis

- data Conflict = Conflict {
  - cfRWA :: !(MaybeX Bool)
  - cfRWB :: !(MaybeX Bool)
  - cfWW :: !(MaybeX Bool)
  }
- getConflict :: (MaybeX Bool, MaybeX Bool, MaybeX Int) -> (MaybeX Bool, MaybeX Bool, MaybeX Int) -> Maybe Conflict
- cycleOne :: forall (nAddrs :: Nat) a writeEnable. (HasCallStack, NFDataX a) => SNat nAddrs -> TdpbramModelConfig writeEnable a -> a -> Seq a -> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) -> (Seq a, a)
- cycleBoth :: forall (nAddrs :: Nat) a writeEnable. (NFDataX a, HasCallStack) => SNat nAddrs -> TdpbramModelConfig writeEnable a -> a -> a -> Seq a -> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) -> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) -> (Seq a, a, a)
- accessRam :: forall (nAddrs :: Nat) a writeEnable. (NFDataX a, HasCallStack) => SNat nAddrs -> (MaybeX writeEnable -> MaybeX Bool) -> (Int -> MaybeX writeEnable -> a -> Seq a -> Seq a) -> MaybeX Int -> MaybeX writeEnable -> a -> Seq a -> (a, Seq a)
- data TdpbramModelConfig writeEnable a = TdpbramModelConfig {
  - tdpIsActiveWriteEnable :: MaybeX writeEnable -> MaybeX Bool
  - tdpMergeWriteEnable :: MaybeX Bool -> MaybeX writeEnable -> MaybeX writeEnable
  - tdpUpdateRam :: Int -> MaybeX writeEnable -> a -> Seq a -> Seq a
  }
- tdpbramModel :: forall (nAddrs :: Nat) (domA :: Domain) (domB :: Domain) a writeEnable. (HasCallStack, KnownNat nAddrs, KnownDomain domA, KnownDomain domB, NFDataX a) => TdpbramModelConfig writeEnable a -> Clock domA -> Signal domA Bool -> Signal domA (Index nAddrs) -> Signal domA writeEnable -> Signal domA a -> Clock domB -> Signal domB Bool -> Signal domB (Index nAddrs) -> Signal domB writeEnable -> Signal domB a -> (Signal domA a, Signal domB a)

# Documentation

data Conflict Source #

Helper used in `getConflict`

Constructors

Conflict |

Fields

- cfRWA :: !(MaybeX Bool)

  Read/Write conflict for output A

- cfRWB :: !(MaybeX Bool)

  Read/Write conflict for output B

- cfWW :: !(MaybeX Bool)

  Write/Write conflict

#### Instances

Instances details

Show Conflict Source # |
Instance details Defined in Clash.Explicit.BlockRam.Model Methods showsPrec :: Int -> Conflict -> ShowS Source # show :: Conflict -> String Source # showList :: [Conflict] -> ShowS Source #

getConflict Source #

Arguments

:: (MaybeX Bool, MaybeX Bool, MaybeX Int) | Port A: enable, write enable, address
-> (MaybeX Bool, MaybeX Bool, MaybeX Int) | Port B: enable, write enable, address
-> Maybe Conflict | `Just` if there is a (potential) write conflict, otherwise `Nothing`

Determines whether there was a write-write or read-write conflict. A conflict occurs when two ports tried to (potentially, in case of undefined values) access the same address and one or both tried to write to it. See documentation of `Conflict` for more information.

cycleOne Source #

Arguments

:: forall (nAddrs :: Nat) a writeEnable. (HasCallStack, NFDataX a) |
=> SNat nAddrs |
-> TdpbramModelConfig writeEnable a |
-> a | Previous value
-> Seq a | Memory
-> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) | Port: enable, address, write enable, write data
-> (Seq a, a) | Updated memory, output value

Step through a cycle of a TDP block RAM where only one clock is active. Like `accessRam`, it accounts for `XException` in all values supplied by the user of the block RAM.

cycleBoth Source #

Arguments

:: forall (nAddrs :: Nat) a writeEnable. (NFDataX a, HasCallStack) |
=> SNat nAddrs |
-> TdpbramModelConfig writeEnable a |
-> a | Previous value for port A
-> a | Previous value for port B
-> Seq a | Memory
-> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) | Port A: enable, address, write enable, write data
-> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) | Port B: enable, address, write enable, write data
-> (Seq a, a, a) | Updated memory, output value A, output value B

Step through a cycle of a TDP block RAM where the clock edges of port A and port B coincided. Like `accessRam`, it accounts for `XException` in all values supplied by the user of the block RAM.

accessRam Source #

Arguments

:: forall (nAddrs :: Nat) a writeEnable. (NFDataX a, HasCallStack) |
=> SNat nAddrs |
-> (MaybeX writeEnable -> MaybeX Bool) | Determine whether a write enable is active
-> (Int -> MaybeX writeEnable -> a -> Seq a -> Seq a) | Update memory with a defined address
-> MaybeX Int | Address
-> MaybeX writeEnable | Byte enable
-> a | Data to write
-> Seq a | Memory to write to
-> (a, Seq a) | (Read after write value, new memory)

Access a RAM and account for undefined values in the address, write enable, and data to write. Return read after write value.

data TdpbramModelConfig writeEnable a Source #

Constructors

TdpbramModelConfig |

Fields

- tdpIsActiveWriteEnable :: MaybeX writeEnable -> MaybeX Bool

  Determine whether a write enable is active

- tdpMergeWriteEnable :: MaybeX Bool -> MaybeX writeEnable -> MaybeX writeEnable

  Merge global enable with write enable

- tdpUpdateRam :: Int -> MaybeX writeEnable -> a -> Seq a -> Seq a

  Update memory with a defined address

tdpbramModel Source #

Arguments

:: forall (nAddrs :: Nat) (domA :: Domain) (domB :: Domain) a writeEnable. (HasCallStack, KnownNat nAddrs, KnownDomain domA, KnownDomain domB, NFDataX a) |
=> TdpbramModelConfig writeEnable a |
-> Clock domA |
-> Signal domA Bool | Enable
-> Signal domA (Index nAddrs) | Address
-> Signal domA writeEnable | Write enable
-> Signal domA a | Write data
-> Clock domB |
-> Signal domB Bool | Enable
-> Signal domB (Index nAddrs) | Address
-> Signal domB writeEnable | Write byte enable
-> Signal domB a | Write data
-> (Signal domA a, Signal domB a) |

Haskell model for a true dual-port block RAM which is polymorphic in its write enables