clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

Copyright | (C) 2017 Google Inc 2019 Myrtle Software Ltd 2025 QBayLogic B.V.
License | BSD2 (see the file LICENSE)
Maintainer | QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell | None
Language | Haskell2010

Clash.Explicit.DDR

Contents

- Internal

Description

We simulate DDR signal by using `Signal`s which have exactly half the period (or double the speed) of our normal `Signal`s.

The primitives in this module can be used to produce or consume DDR signals.

DDR signals are not meant to be used internally in a design, but only to communicate with the outside world.

In some cases hardware specific DDR IN registers can be inferred by synthesis tools from these generic primitives. But to be sure your design will synthesize to dedicated hardware resources use the functions from Clash.Intel.DDR or Clash.Xilinx.DDR.

Synopsis

- ddrIn :: forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior) (polarity :: ResetPolarity) (slow :: Domain). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> (a, a, a) -> Signal fast a -> Signal slow (a, a)
- ddrOut :: forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior) (polarity :: ResetPolarity) (slow :: Domain). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> Signal slow (a, a) -> Signal fast a
- ddrIn# :: forall a (slow :: Domain) (fast :: Domain) (fPeriod :: Nat) (polarity :: ResetPolarity) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> a -> a -> Signal fast a -> Signal slow (a, a)
- ddrOut# :: forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior) (polarity :: ResetPolarity) (slow :: Domain). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> Signal slow a -> Signal slow a -> Signal fast a

# Documentation

ddrIn Source #

Arguments

:: forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior) (polarity :: ResetPolarity) (slow :: Domain). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) |
=> Clock slow |
-> Reset slow |
-> Enable slow |
-> (a, a, a) | Reset values
-> Signal fast a | DDR input signal
-> Signal slow (a, a) | Normal speed output pair `(o0, o1)`

DDR input primitive

Consumes a DDR input signal and produces a regular signal containing a pair of values.

Data is clocked in on both edges of the clock signal. We can discern the active edge of the clock and the other edge. When the domain has the rising edge as the active edge (which is the most common), this means that the rising edge is the active edge and the falling edge is the other edge.

Of the output pair `(o0, o1)`, `o0` is the data clocked in on the other edge and `o1` is the data clocked in on the active edge, and `o0` comes before `o1` in time. With a domain where the rising edge is the active edge, this means `o0` is clocked in on the falling clock edge and `o1` is clocked in on the rising clock edge. For a domain with the falling edge as the active edge, this is the other way around, but `o0` still comes before `o1` in time.

    >>> sampleN 5 $ ddrIn systemClockGen systemResetGen enableGen (-1,-2,-3) (fromList [0..10] :: Signal Fast Int)
    [(-1,-2),(-1,-2),(-3,2),(3,4),(5,6)]

ddrOut Source #

Arguments

:: forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior) (polarity :: ResetPolarity) (slow :: Domain). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) |
=> Clock slow |
-> Reset slow |
-> Enable slow |
-> a | Reset value
-> Signal slow (a, a) | Normal speed input pair `(i0, i1)`
-> Signal fast a | DDR output signal

DDR output primitive

Produces a DDR output signal from a normal signal of pairs of input.

Data is clocked out on both edges of the clock signal. We can discern the active edge of the clock and the other edge. When the domain has the rising edge as the active edge (which is the most common), this means that the rising edge is the active edge and the falling edge is the other edge.

Of the input pair `(i0, i1)`, `i0` is the data clocked out on the active edge and `i1` is the data clocked out on the other edge, and `i0` comes before `i1` in time. With a domain where the rising edge is the active edge, this means `i0` is clocked out on the rising clock edge and `i1` is clocked out on the falling clock edge. For a domain with the falling edge as the active edge, this is the other way around, but `i0` still comes before `i1` in time.

    >>> sampleN 7 (ddrOut systemClockGen systemResetGen enableGen (-1) (fromList [(0,1),(2,3),(4,5)]) :: Signal Fast Int)
    [-1,-1,-1,2,3,4,5]

# Internal

ddrIn# :: forall a (slow :: Domain) (fast :: Domain) (fPeriod :: Nat) (polarity :: ResetPolarity) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> a -> a -> Signal fast a -> Signal slow (a, a) Source #

ddrOut# :: forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge) (reset :: ResetKind) (init :: InitBehavior) (polarity :: ResetPolarity) (slow :: Domain). (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> Signal slow a -> Signal slow a -> Signal fast a Source #