clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

Copyright | (C) 2015-2016 University of Twente 2017 Google Inc. 2019 Myrtle Software Ltd 2021-2022 QBayLogic B.V.
License | BSD2 (see the file LICENSE)
Maintainer | QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell | Trustworthy
Language | Haskell2010

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Clash.Explicit.RAM

Contents

- RAM synchronized to an arbitrary clock
- Internal

Description

RAM primitives with a combinational read port.

Synopsis

- asyncRam :: forall addr (wdom :: Domain) (rdom :: Domain) a (n :: Nat). (Enum addr, NFDataX addr, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) => Clock wdom -> Clock rdom -> Enable wdom -> SNat n -> Signal rdom addr -> Signal wdom (Maybe (addr, a)) -> Signal rdom a
- asyncRamPow2 :: forall (wdom :: Domain) (rdom :: Domain) (n :: Nat) a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) => Clock wdom -> Clock rdom -> Enable wdom -> Signal rdom (Unsigned n) -> Signal wdom (Maybe (Unsigned n, a)) -> Signal rdom a
- asyncRam# :: forall (wdom :: Domain) (rdom :: Domain) (n :: Nat) a. (HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) => Clock wdom -> Clock rdom -> Enable wdom -> SNat n -> Signal rdom Int -> Signal wdom Bool -> Signal wdom Int -> Signal wdom a -> Signal rdom a

# RAM synchronized to an arbitrary clock

asyncRam Source #

Arguments

:: forall addr (wdom :: Domain) (rdom :: Domain) a (n :: Nat). (Enum addr, NFDataX addr, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) |
=> Clock wdom | `Clock` to which the write port of the RAM is synchronized
-> Clock rdom | `Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom | `Enable` line for the write port
-> SNat n | Size `n` of the RAM
-> Signal rdom addr | Read address `r`
-> Signal wdom (Maybe (addr, a)) | (write address `w`, value to write)
-> Signal rdom a | Value of the RAM at address `r`

Create a RAM with space for `n` elements

- NB: Initial content of the RAM is undefined, reading it will throw an `XException`

### See also:

- See Clash.Explicit.BlockRam for more information on how to use a RAM.

asyncRamPow2 Source #

Arguments

:: forall (wdom :: Domain) (rdom :: Domain) (n :: Nat) a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) |
=> Clock wdom | `Clock` to which the write port of the RAM is synchronized
-> Clock rdom | `Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom | `Enable` line for the write port
-> Signal rdom (Unsigned n) | Read address `r`
-> Signal wdom (Maybe (Unsigned n, a)) | (write address `w`, value to write)
-> Signal rdom a | Value of the RAM at address `r`

Create a RAM with space for 2^`n` elements

- NB: Initial content of the RAM is undefined, reading it will throw an `XException`

### See also:

- See Clash.Prelude.BlockRam for more information on how to use a RAM.

# Internal

asyncRam# Source #

Arguments

:: forall (wdom :: Domain) (rdom :: Domain) (n :: Nat) a. (HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) |
=> Clock wdom | `Clock` to which the write port of the RAM is synchronized
-> Clock rdom | `Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom | `Enable` line for the write port
-> SNat n | Size `n` of the RAM
-> Signal rdom Int | Read address `r`
-> Signal wdom Bool | Write enable
-> Signal wdom Int | Write address `w`
-> Signal wdom a | Value to write (at address `w`)
-> Signal rdom a | Value of the RAM at address `r`

RAM primitive