clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

# clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

- Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
- Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
- Higher-order functions, with type inference, result in designs that are fully parametric by default.
- Synchronous sequential circuit design based on streams of values, called `Signal`s, lead to natural descriptions of feedback loops.
- Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

- Prelude library containing datatypes and functions for circuit design

To use the library:

- Import Clash.Prelude
- Alternatively, if you want to explicitly route clock and reset ports, for more straightforward multi-clock designs, you can import the Clash.Explicit.Prelude module. Note that you should not import Clash.Prelude and Clash.Explicit.Prelude at the same time as they have overlapping definitions.

A preliminary version of a tutorial can be found in Clash.Tutorial, for a general overview of the library you should however check out Clash.Prelude. Some circuit examples can be found in Clash.Examples.

Modules

clash-prelude-1.8.4

- Clash
  Submodules
  - Annotations
    Submodules
    - Clash.Annotations.BitRepresentation
      Submodules
      - Clash.Annotations.BitRepresentation.Deriving
      - Clash.Annotations.BitRepresentation.Internal
      - Clash.Annotations.BitRepresentation.Util
    - Clash.Annotations.Primitive
    - Clash.Annotations.SynthesisAttributes
    - Clash.Annotations.TH
    - Clash.Annotations.TopEntity
  - Class
    Submodules
    - Clash.Class.AutoReg
      Submodules
      - Clash.Class.AutoReg.Internal
    - Clash.Class.BitPack
      Submodules
      - Clash.Class.BitPack.BitIndex
      - Clash.Class.BitPack.BitReduction
      - Clash.Class.BitPack.Internal
        Submodules
        - Clash.Class.BitPack.Internal.TH
    - Clash.Class.Counter
      Submodules
      - Clash.Class.Counter.Internal
      - Clash.Class.Counter.TH
    - Clash.Class.Exp
    - Clash.Class.HasDomain
      Submodules
      - Clash.Class.HasDomain.CodeGen
      - Clash.Class.HasDomain.Common
      - Clash.Class.HasDomain.HasSingleDomain
      - Clash.Class.HasDomain.HasSpecificDomain
    - Clash.Class.Num
    - Clash.Class.Parity
    - Clash.Class.Resize
  - Clash.Clocks
  - Clash.Examples
    Submodules
    - Clash.Examples.Internal
  - Explicit
    Submodules
    - Clash.Explicit.BlockRam
      Submodules
      - Clash.Explicit.BlockRam.Blob
      - Clash.Explicit.BlockRam.File
      - Clash.Explicit.BlockRam.Internal
      - Clash.Explicit.BlockRam.Model
    - Clash.Explicit.DDR
    - Clash.Explicit.Mealy
    - Clash.Explicit.Moore
    - Clash.Explicit.Prelude
      Submodules
      - Clash.Explicit.Prelude.Safe
    - Clash.Explicit.RAM
    - Clash.Explicit.ROM
      Submodules
      - Clash.Explicit.ROM.Blob
      - Clash.Explicit.ROM.File
    - Clash.Explicit.Reset
    - Clash.Explicit.Signal
      Submodules
      - Clash.Explicit.Signal.Delayed
    - Clash.Explicit.SimIO
    - Clash.Explicit.Synchronizer
    - Clash.Explicit.Testbench
    - Clash.Explicit.Verification
  - Clash.HaskellPrelude
  - Clash.Hidden
  - Intel
    Submodules
    - Clash.Intel.ClockGen
    - Clash.Intel.DDR
  - Clash.Magic
  - Clash.NamedTypes
  - Num
    Submodules
    - Clash.Num.Erroring
    - Clash.Num.Overflowing
    - Clash.Num.Saturating
    - Clash.Num.Wrapping
    - Clash.Num.Zeroing
  - Clash.Prelude
    Submodules
    - Clash.Prelude.BlockRam
      Submodules
      - Clash.Prelude.BlockRam.Blob
      - Clash.Prelude.BlockRam.File
    - Clash.Prelude.DataFlow
    - Clash.Prelude.Mealy
    - Clash.Prelude.Moore
    - Clash.Prelude.RAM
    - Clash.Prelude.ROM
      Submodules
      - Clash.Prelude.ROM.Blob
      - Clash.Prelude.ROM.File
    - Clash.Prelude.Safe
    - Clash.Prelude.Testbench
  - Promoted
    Submodules
    - Clash.Promoted.Nat
      Submodules
      - Clash.Promoted.Nat.Literals
      - Clash.Promoted.Nat.TH
      - Clash.Promoted.Nat.Unsafe
    - Clash.Promoted.Symbol
  - Clash.Signal
    Submodules
    - Clash.Signal.BiSignal
    - Clash.Signal.Bundle
    - Clash.Signal.Delayed
      Submodules
      - Clash.Signal.Delayed.Bundle
      - Clash.Signal.Delayed.Internal
    - Clash.Signal.Internal
      Submodules
      - Clash.Signal.Internal.Ambiguous
    - Clash.Signal.Trace
  - Sized
    Submodules
    - Clash.Sized.BitVector
    - Clash.Sized.Fixed
    - Clash.Sized.Index
    - Internal
      Submodules
      - Clash.Sized.Internal.BitVector
      - Clash.Sized.Internal.Index
      - Clash.Sized.Internal.Mod
      - Clash.Sized.Internal.Signed
      - Clash.Sized.Internal.Unsigned
    - Clash.Sized.RTree
    - Clash.Sized.Signed
    - Clash.Sized.Unsigned
    - Clash.Sized.Vector
      Submodules
      - Clash.Sized.Vector.ToTuple
  - Clash.Tutorial
  - Clash.Verification
    Submodules
    - Clash.Verification.DSL
    - Clash.Verification.Internal
  - Clash.XException
    Submodules
    - Clash.XException.Internal
    - Clash.XException.MaybeX
    - Clash.XException.TH
  - Xilinx
    Submodules
    - Clash.Xilinx.ClockGen
    - Clash.Xilinx.DDR