clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

Copyright | (C) 2015-2016 University of Twente 2017 Google Inc. 2019 Myrtle Software Ltd 2021-2022 QBayLogic B.V.
License | BSD2 (see the file LICENSE)
Maintainer | QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell | Trustworthy
Language | Haskell2010

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Clash.Explicit.ROM

Contents

- Synchronous ROM synchronized to an arbitrary clock
- Internal

Description

ROMs

Synopsis

- rom :: forall (dom :: Domain) (n :: Nat) a addr. (KnownDomain dom, KnownNat n, NFDataX a, Enum addr) => Clock dom -> Enable dom -> Vec n a -> Signal dom addr -> Signal dom a
- romPow2 :: forall (dom :: Domain) (n :: Nat) a. (KnownDomain dom, KnownNat n, NFDataX a) => Clock dom -> Enable dom -> Vec (2 ^ n) a -> Signal dom (Unsigned n) -> Signal dom a
- rom# :: forall (dom :: Domain) (n :: Nat) a. (KnownDomain dom, KnownNat n, NFDataX a) => Clock dom -> Enable dom -> Vec n a -> Signal dom Int -> Signal dom a

# Synchronous ROM synchronized to an arbitrary clock

rom Source #

Arguments

:: forall (dom :: Domain) (n :: Nat) a addr. (KnownDomain dom, KnownNat n, NFDataX a, Enum addr) |
=> Clock dom | `Clock` to synchronize to
-> Enable dom | `Enable` line
-> Vec n a | ROM content, also determines the size, `n`, of the ROM NB: MUST be a constant
-> Signal dom addr | Read address `r`
-> Signal dom a | The value of the ROM at address `r` from the previous clock cycle

A ROM with a synchronous read port, with space for `n` elements

- NB: Read value is delayed by 1 cycle
- NB: Initial output value is undefined, reading it will throw an `XException`

### See also:

- See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs.
- A large `Vec` for the content may be too inefficient, depending on how it is constructed. See `romFile` and `romBlob` for different approaches that scale well.

romPow2 Source #

Arguments

:: forall (dom :: Domain) (n :: Nat) a. (KnownDomain dom, KnownNat n, NFDataX a) |
=> Clock dom | `Clock` to synchronize to
-> Enable dom | `Enable` line
-> Vec (2 ^ n) a | ROM content NB: MUST be a constant
-> Signal dom (Unsigned n) | Read address `r`
-> Signal dom a | The value of the ROM at address `r` from the previous clock cycle

A ROM with a synchronous read port, with space for 2^`n` elements

- NB: Read value is delayed by 1 cycle
- NB: Initial output value is undefined, reading it will throw an `XException`

### See also:

- See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs.
- A large `Vec` for the content may be too inefficient, depending on how it is constructed. See `romFilePow2` and `romBlobPow2` for different approaches that scale well.

# Internal

rom# Source #

Arguments

:: forall (dom :: Domain) (n :: Nat) a. (KnownDomain dom, KnownNat n, NFDataX a) |
=> Clock dom | `Clock` to synchronize to
-> Enable dom | `Enable` line
-> Vec n a | ROM content, also determines the size, `n`, of the ROM NB: MUST be a constant
-> Signal dom Int | Read address `rd`
-> Signal dom a | The value of the ROM at address `rd` from the previous clock cycle

ROM primitive