clash-prelude-1.8.4: Clash: a functional hardware description language - Prelude library

Copyright | (C) 2015-2016 University of Twente 2016-2019 Myrtle Software Ltd 2017 Google Inc. 2021-2022 QBayLogic B.V.
License | BSD2 (see the file LICENSE)
Maintainer | QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell | Safe
Language | Haskell2010

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Clash.Explicit.Synchronizer

Contents

- Bit-synchronizers
- Word-synchronizers

Description

Synchronizer circuits for safe clock domain crossings

Synopsis

- dualFlipFlopSynchronizer :: forall a (dom1 :: Domain) (dom2 :: Domain). (NFDataX a, KnownDomain dom1, KnownDomain dom2) => Clock dom1 -> Clock dom2 -> Reset dom2 -> Enable dom2 -> a -> Signal dom1 a -> Signal dom2 a
- asyncFIFOSynchronizer :: forall (wdom :: Domain) (rdom :: Domain) (addrSize :: Natural) a. (KnownDomain wdom, KnownDomain rdom, 2 <= addrSize, NFDataX a) => SNat addrSize -> Clock wdom -> Clock rdom -> Reset wdom -> Reset rdom -> Enable wdom -> Enable rdom -> Signal rdom Bool -> Signal wdom (Maybe a) -> (Signal rdom a, Signal rdom Bool, Signal wdom Bool)

# Bit-synchronizers

dualFlipFlopSynchronizer Source #

Arguments

:: forall a (dom1 :: Domain) (dom2 :: Domain). (NFDataX a, KnownDomain dom1, KnownDomain dom2) |
=> Clock dom1 | `Clock` to which the incoming data is synchronized
-> Clock dom2 | `Clock` to which the outgoing data is synchronized
-> Reset dom2 | `Reset` for registers on the outgoing domain
-> Enable dom2 | `Enable` for registers on the outgoing domain
-> a | Initial value of the two synchronization registers
-> Signal dom1 a | Incoming data
-> Signal dom2 a | Outgoing, synchronized, data

Synchronizer based on two sequentially connected flip-flops.

- NB: This synchronizer can be used for bit-synchronization.

- NB: Although this synchronizer does reduce metastability, it does not guarantee the proper synchronization of a whole word. For example, given that the output is sampled twice as fast as the input is running, and we have two samples in the input stream that look like:

      [0111,1000]

  But the circuit driving the input stream has a longer propagation delay on msb compared to the lsbs. What can happen is an output stream that looks like this:

      [0111,0111,0000,1000]

  Where the level-change of the msb was not captured, but the level change of the lsbs were.

  If you want to have safe word-synchronization use `asyncFIFOSynchronizer`.

# Word-synchronizers

asyncFIFOSynchronizer Source #

Arguments

:: forall (wdom :: Domain) (rdom :: Domain) (addrSize :: Natural) a. (KnownDomain wdom, KnownDomain rdom, 2 <= addrSize, NFDataX a) |
=> SNat addrSize | Size of the internally used addresses, the FIFO contains `2^addrSize` elements.
-> Clock wdom | `Clock` to which the write port is synchronized
-> Clock rdom | `Clock` to which the read port is synchronized
-> Reset wdom |
-> Reset rdom |
-> Enable wdom |
-> Enable rdom |
-> Signal rdom Bool | Read request
-> Signal wdom (Maybe a) | Element to insert
-> (Signal rdom a, Signal rdom Bool, Signal wdom Bool) | (Oldest element in the FIFO, `empty` flag, `full` flag)

Synchronizer implemented as a FIFO around a synchronous RAM. Based on the design described in Clash.Tutorial, which is itself based on the design described in http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf. However, this FIFO uses a synchronous dual-ported RAM which, unlike those designs using RAM with an asynchronous read port, is nearly guaranteed to actually synthesize into one of the dual-ported RAMs found on most FPGAs.

NB: This synchronizer can be used for word-synchronization. NB: This synchronizer will only work safely when you set up the proper bus skew and maximum delay constraints inside your synthesis tool for the clock domain crossings of the gray pointers.