RS-FF, D-FF and other basic flip-flop components

# Basic flip-flops

# RS flip-flop

RS flip-flop

Store input using an RS flip-flop.

## Equivalent circuit:

RS flip-flop

## Truth table:

Input | Output
S | R | Q | ~Q
L | L | Q(n-1) | ~Q(n-1)
H | L | H | L
L | H | L | H
H | H | L | L

## Properties:

Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level

Strictly, the behavior of RS flip-flops is not defined on R=S=1 and the situation when it's changed to R=S=0, but this component outputs Q=1 and steady.

# JK flip-flop

JK flip-flop

Store input using an edge triggered JK flip-flop.

## Equivalent circuit:

JK flip-flop

## Truth table:

Input | Output
J | K | CK | Q | ~Q
L | L | ↑(↓) | Q(n-1) | ~Q(n-1)
H | L | H | L
L | H | L | H
H | H | ~Q(n-1) | Q(n-1)

## Properties:

Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level

# D flip-flop

D flip-flop

Store input using a D flip-flop.

## Equivalent circuit:

D flip-flop

## Truth table:

Input | Output
D | CK | Q | ~Q
H | ↑(↓) | H | L
L | L | H

## Properties:

Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level

# T flip-flop

T flip-flop

Toggle output using a T flip-flop.

## Equivalent circuit:

T flip-flop

## Truth table:

Input | Output
CK | Q | ~Q
↑(↓) | ~Q(n-1) | Q(n-1)

## Properties:

Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level