Shift register components composed of flip-flops

# Shift registers

# SISO shift register

SISO shift register

Serial input and output shift register based on a series of D flip-flop

## Truth table:

Input | Output
D | CK | Q | ~Q
X | ↑(↓) | D(n-m) | ~D(n-m)

m: A number of bits of a shift register

## Properties:

Number of bits | A number of steps of D flip-flops contained in a shift register
Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level

# SIPO shift register

SIPO shift register

Serial input and paralell output shift register based on a series of D flip-flop

## Equivalent circuit:

SIPO shift register

## Truth table:

Input | Output
RST | D | CK | Q0 | Q{m}
L | X | ↑(↓) | D(n-1) | Q{m-1}(n-1)
H | X | L | L

## Properties:

Number of bits | A number of steps of D flip-flops contained in a shift register
Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level

# PISO shift register

PISO shift register

Paralell input and serial output shift register based on D flip-flop

## Truth table:

Mode | Input | Output
W/S | D{m} | CK | Q0S | Q{m}S | Q | ~Q
Write | L | X | ↑(↓) | D0(n-1) | D{m}(n-1) | Q{p-1}S | ~Q{p-1}S
Shift | H | Q0S(n-1) | Q{m-1}S(n-1)

p: A number of bits of a shift register

Q{m}S are state variables in components, so they don't have output ports

## Properties:

Number of bits | A number of steps of D flip-flops contained in a shift register
Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level

# PIPO shift register

PIPO shift register

Paralell input and output shift register based on D flip-flop

## Truth table:

Mode | Input | Output
S0 | S1 | SR | D{m} | SL | CK | Q0 | Q{m} | Q{p}
Hold | L | L | X | X | X | ↑(↓) | Q0(n-1) | Q{m}(n-1) | Q{p}(n-1)
Shift left | L | H | Q1(n-1) | Q{m+1}(n-1) | SL(n-1)
Shift right | H | L | SR(n-1) | Q{m-1}(n-1) | Q{p-1}(n-1)
Write | H | H | D0(n-1) | D{m}(n-1) | D{p}(n-1)

p: A number of bits of a shift register

## Properties:

Number of bits | A number of steps of D flip-flops contained in a shift register
Trigger type | Type of clock signals. Positive edge (↑) or Negative edge (↓)
Propagation delay
tPHL | Delays when output is changed from H level to L level
tPLH | Delays when output is changed from L level to H level