2024-09-05  H.J. Lu  <hjl.tools@gmail.com>

	Backported from master:
	2024-09-03  H.J. Lu  <hjl.tools@gmail.com>

	PR ipa/116410
	* ipa-modref.cc (analyze_parms): Always analyze function parameter
	for LTO.

2024-09-05  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-09-03  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/116501
	* gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
	In the last_ovf case, use build_zero_cst operand not just when
	TYPE_UNSIGNED (typeN), but also when precN >= 0.

2024-09-05  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-08-07  Jakub Jelinek  <jakub@redhat.com>

	PR c++/116219
	* gimple-expr.cc (remove_suffix): Formatting fixes.
	(create_tmp_var_name): Don't call clean_symbol_name.
	* gimplify.cc (gimplify_init_constructor): When promoting automatic
	DECL_NAMELESS vars to static, don't preserve their DECL_NAME.

2024-09-04  Andrew Carlotti  <andrew.carlotti@arm.com>

	PR target/112108
	* config/aarch64/aarch64-builtins.cc (handle_arm_acle_h): Remove
	feature check at initialisation.
	(aarch64_general_check_builtin_call): Check ls64 intrinsics.
	* config/aarch64/arm_acle.h: (data512_t) Make always available.

2024-09-04  Andrew Carlotti  <andrew.carlotti@arm.com>

	PR target/112108
	* config/aarch64/aarch64-builtins.cc (aarch64_init_memtag_builtins):
	Define intrinsic names directly.
	(aarch64_general_init_builtins): Move memtag intialisation...
	(handle_arm_acle_h): ...to here, and remove feature check.
	(aarch64_general_check_builtin_call): Check memtag intrinsics.
	* config/aarch64/arm_acle.h (__arm_mte_create_random_tag)
	(__arm_mte_exclude_tag, __arm_mte_ptrdiff)
	(__arm_mte_increment_tag, __arm_mte_set_tag, __arm_mte_get_tag):
	Remove.

2024-09-04  Andrew Carlotti  <andrew.carlotti@arm.com>

	PR target/112108
	* config/aarch64/aarch64-builtins.cc (aarch64_init_tme_builtins):
	Define intrinsic names directly.
	(aarch64_general_init_builtins): Move tme initialisation...
	(handle_arm_acle_h): ...to here, and remove feature check.
	(aarch64_general_check_builtin_call): Check tme intrinsics.
	* config/aarch64/arm_acle.h (__tstart, __tcommit, __tcancel)
	(__ttest): Remove.
	(_TMFAILURE_*): Define unconditionally.

2024-09-04  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-sve-builtins.cc (check_builtin_call)
	(expand_builtin): Update calls to the below.
	(report_missing_extension, report_missing_registers)
	(check_required_extensions): Move out of aarch64_sve namespace,
	rename, and move into...
	* config/aarch64/aarch64-builtins.cc (aarch64_report_missing_extension)
	(aarch64_report_missing_registers)
	(aarch64_check_required_extensions) ...here.
	* config/aarch64/aarch64-protos.h (aarch64_check_required_extensions):
	Add prototype.

2024-09-04  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-sve-builtins.cc
	(check_required_registers): Remove target check and rename to...
	(report_missing_registers): ...this.
	(check_required_extensions): Refactor.

2024-09-03  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/avx512fp16intrin.h
	(_mm512_mask_fpclass_ph_mask): Correct mask type to __mmask32.
	(_mm512_fpclass_ph_mask): Ditto.

2024-09-02  liuhongt  <hongtao.liu@intel.com>

	Backported from master:
	2024-08-30  liuhongt  <hongtao.liu@intel.com>

	PR target/116512
	* config/i386/i386.cc (ix86_check_avx_upper_register): Iterate
	subrtx to scan for avx upper register.
	(ix86_check_avx_upper_stores): Inline old
	ix86_check_avx_upper_register.
	(ix86_avx_u128_mode_needed): Ditto, and replace
	FOR_EACH_SUBRTX with call to new
	ix86_check_avx_upper_register.

2024-08-22  liuhongt  <hongtao.liu@intel.com>

	Backported from master:
	2024-08-22  liuhongt  <hongtao.liu@intel.com>

	* config/i386/i386-options.cc (ix86_option_override_internal):
	set ix86_{move_max,store_max} to PVW_AVX256 when TARGET_AVX
	instead of PVW_AVX128.

2024-08-18  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-08-18  Georg-Johann Lay  <avr@gjlay.de>

	PR target/116407
	* config/avr/avr.md (*dec-and-branchhi!=-1.l.clobber):
	Increase the additional jump offset to 2 words.

2024-08-18  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-08-18  Georg-Johann Lay  <avr@gjlay.de>

	PR target/116407
	* config/avr/avr-protos.h (avr_jump_mode): Add an int argument.
	* config/avr/avr.cc (avr_jump_mode): Add an int argument to increase
	the computed jump offset of backwards branches.
	* config/avr/avr.md (*dec-and-branchhi!=-1, *dec-and-branchsi!=-1):
	Increase the jump offset used by avr_jump_mode() as needed.

2024-08-17  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-08-17  Georg-Johann Lay  <avr@gjlay.de>

	PR target/116390
	* config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix
	output templates for the reg_base == reg_src and
	reg_src == reg_base - 2 cases.

2024-08-16  Georg-Johann Lay  <avr@gjlay.de>

	PR target/85624
	* config/avr/avr.md (*clrmemqi*): Use HImode for alignment operand.

2024-08-16  Lingling Kong  <lingling.kong@intel.com>

	* config/i386/sse.md (vpmadd52<vpmadd52type><mode>):
	Prohibit egpr for vex version.
	(vpdpbusd_<mode>): Ditto.
	(vpdpbusds_<mode>): Ditto.
	(vpdpwssd_<mode>): Ditto.
	(vpdpwssds_<mode>): Ditto.
	(*vcvtneps2bf16_v4sf): Ditto.
	(*vcvtneps2bf16_v8sf): Ditto.
	(vpdp<vpdotprodtype>_<mode>): Ditto.
	(vbcstnebf162ps_<mode>): Ditto.
	(vbcstnesh2ps_<mode>): Ditto.
	(vcvtnee<bf16_ph>2ps_<mode>): Ditto.
	(vcvtneo<bf16_ph>2ps_<mode>): Ditto.
	(vpdp<vpdpwprodtype>_<mode>): Ditto.

2024-08-16  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/115464
	* config/aarch64/aarch64-sve-builtins-base.cc
	(svset_neonq_impl::expand): Use force_subreg instead of
	lowpart_subreg.

2024-08-16  Richard Sandiford  <richard.sandiford@arm.com>

	Backported from master:
	2024-06-13  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/115464
	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
	to fold two subregs together if their relationship isn't known
	at compile time.
	* explow.h (force_subreg): Declare.
	* explow.cc (force_subreg): New function.
	* config/aarch64/aarch64-sve-builtins-base.cc
	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.

2024-08-16  liuhongt  <hongtao.liu@intel.com>

	Backported from master:
	2024-08-14  liuhongt  <hongtao.liu@intel.com>

	PR target/116174
	* config/i386/i386.cc (ix86_align_loops): Move this to ..
	* config/i386/i386-features.cc (ix86_align_loops): .. here.
	(class pass_align_tight_loops): New class.
	(make_pass_align_tight_loops): New function.
	* config/i386/i386-passes.def: Insert pass_align_tight_loops
	after pass_insert_endbr_and_patchable_area.
	* config/i386/i386-protos.h (make_pass_align_tight_loops): New
	declare.

2024-08-14  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	Backported from master:
	2024-08-14  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390-builtin-types.def (BT_FN_UV16QI_UV2DI_UV2DI):
	New.
	(BT_FN_UV16QI_UV2DI_UV2DI_UV16QI): New.
	* config/s390/s390-builtins.def (s390_vgfmg_128): New.
	(s390_vgfmag_128): New.
	* config/s390/vecintrin.h (vec_gfmsum_128): Use s390_vgfmg_128.
	(vec_gfmsum_accum_128): Use s390_vgfmag_128.

2024-08-13  Michael Meissner  <meissner@linux.ibm.com>

	* config.gcc (powerpc*-*-*): Add support for power11.
	* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
	* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
	* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
	* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
	* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
	* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
	_ARCH_PWR11 if -mcpu=power11.
	* config/rs6000/rs6000-cpus.def (POWER11_MASKS_SERVER): New define.
	(POWERPC_MASKS): Add power11.
	(power11 cpu): Add power11 definition.
	* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
	* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
	* config/rs6000/rs6000-tables.opt: Regenerate.
	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
	support.
	(rs6000_machine_from_flags): Likewise.
	(rs6000_reassociation_width): Likewise.
	(rs6000_adjust_cost): Likewise.
	(rs6000_issue_rate): Likewise.
	(rs6000_sched_reorder): Likewise.
	(rs6000_sched_reorder2): Likewise.
	(rs6000_register_move_cost): Likewise.
	(rs6000_opt_masks): Likewise.
	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
	* config/rs6000/rs6000.md (cpu attribute): Add power11.
	* config/rs6000/rs6000.opt (-mpower11): Add internal power11 flag.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
	* config/rs6000/power10.md (all reservations): Add power11 support.

2024-08-09  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-08-09  Jakub Jelinek  <jakub@redhat.com>

	PR target/116287
	* config/i386/i386.cc (ix86_fold_builtin) <case IX86_BUILTIN_BEXTR32>:
	When folding into zero without checking whether first argument is
	constant, use omit_one_operand.
	(ix86_fold_builtin) <case IX86_BUILTIN_BZHI32>: Likewise.

2024-08-08  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-08-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/116295
	* config/avr/avr.cc (Mem_Insn::Mem_Insn): Don't consider MEMs
	that are avr_mem_memx_p or avr_load_libgcc_p.

2024-08-06  John David Anglin  <danglin@gcc.gnu.org>

	PR target/113384
	* config/pa/pa.cc (hppa_legitimize_address): Add check to
	ensure constant is an integral multiple of shift the value.

2024-08-06  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-08-06  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/116224
	* wide-int.cc (wi::mul_internal): If prec isn't multiple of
	HOST_BITS_PER_WIDE_INT, for need_overflow checking only look at
	the least significant prec bits starting with r[half_blocks_needed].

2024-08-06  Andrew Pinski  <quic_apinski@quicinc.com>

	Backported from master:
	2024-08-06  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/116189
	* config/sh/sh.cc (sh_recog_treg_set_expr): Don't call make_insn_raw,
	make the insn with a fake uid.

2024-08-05  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-07-25  Christoph Müllner  <christoph.muellner@vrull.eu>

	PR target/116033
	* config/riscv/thead.cc (th_memidx_classify_address_modify):
	Fix mode test.

2024-08-02  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/116156
	* tree-ssa-forwprop.cc (pass_forwprop::execute): Don't add
	uses if the statement was a debug statement.

2024-08-02  liuhongt  <hongtao.liu@intel.com>

	Backported from master:
	2024-07-30  liuhongt  <hongtao.liu@intel.com>

	PR target/116043
	* config/i386/constraints.md (Bk): Refine to
	define_special_memory_constraint.

2024-08-02  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/prfchiintrin.h
	(_m_prefetchit0): Add macro for non-optimized option.
	(_m_prefetchit1): Ditto.

2024-08-02  Yang Yujie  <yangyujie@loongson.cn>

	Backported from master:
	2024-08-02  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/gen-evolution.awk: Do not use
	"length()" to compute the size of an array.

2024-08-01  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-08-01  Jakub Jelinek  <jakub@redhat.com>

	PR target/115981
	* config/i386/sse.md
	(*<extract_type>_vinsert<shuffletype><extract_suf>_0): Swap the
	first two VEC_MERGE operands, renumber match_operands and test
	for 0xF or 0x3 rather than 0xFFF0 or 0xFC immediate.

2024-08-01  Release Manager

	* GCC 14.2.0 released.

2024-07-30  Lingling Kong  <lingling.kong@intel.com>

	PR target/115978
	* config/i386/driver-i386.cc (host_detect_local_cpu):  Enable
	APX_F only for 64-bit codegen.
	* config/i386/i386-options.cc (DEF_PTA):  Skip PTA_APX_F if
	not in 64-bit mode.

2024-07-29  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-24  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/116057
	* tree-ssa-ccp.cc (likely_value): Also walk CTORs in stmt
	operands to look for constants.

2024-07-29  Jan Hubicka  <hubicka@ucw.cz>

	PR ipa/116055
	* ipa-modref.cc (analyze_function): Do not ICE when flags regress.

2024-07-29  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/avx512dqintrin.h
	(_mm_mask_fpclass_ss_mask): Correct operand order.
	(_mm_mask_fpclass_sd_mask): Ditto.
	(_mm256_maskz_reduce_round_ss): Use __builtin_ia32_reducess_mask_round
	instead of __builtin_ia32_reducesd_mask_round.
	(_mm_reduce_round_sd): Use -1 as mask since it is non-mask.
	(_mm_reduce_round_ss): Ditto.
	* config/i386/avx512vlbwintrin.h
	(_mm256_mask_alignr_epi8): Correct operand usage.
	(_mm_mask_alignr_epi8): Ditto.
	* config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto.

2024-07-24  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-07-24  Christoph Müllner  <christoph.muellner@vrull.eu>

	PR target/116035
	* config/riscv/bitmanip.md: Disable zero_extendsidi2_bitmanip
	for XTheadMemIdx.

2024-07-23  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-07-23  Jakub Jelinek  <jakub@redhat.com>
		    Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/116034
	* tree-ssa.cc (maybe_rewrite_mem_ref_base): Only use IMAGPART_EXPR
	if MEM_REF offset is equal to element type size.

2024-07-23  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/i386.md (prefetchi): Change to %a.

2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	Backported from master:
	2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	PR ipa/111613
	* ipa-modref.cc (analyze_parms): Do not preserve EAF_NO_DIRECT_READ and
	EAF_NO_INDIRECT_READ from past flags.

2024-07-22  Peter Bergner  <bergner@linux.ibm.com>

	Backported from master:
	2024-07-17  Peter Bergner  <bergner@linux.ibm.com>

	PR target/114759
	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Disallow
	CPUs and ABIs that do no support the ROP protection insns.
	* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Remove now
	unneeded tests.
	(rs6000_emit_prologue): Likewise.
	Remove unneeded gcc_assert.
	(rs6000_emit_epilogue): Likewise.
	* config/rs6000/rs6000.md: Likewise.

2024-07-22  Peter Bergner  <bergner@linux.ibm.com>

	Backported from master:
	2024-07-17  Peter Bergner  <bergner@linux.ibm.com>

	PR target/114759
	* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Use TARGET_POWER8.
	(rs6000_emit_prologue): Likewise.
	* config/rs6000/rs6000.md (hashchk): Likewise.
	(hashst): Likewise.
	Fix whitespace.

2024-07-22  Peter Bergner  <bergner@linux.ibm.com>

	Backported from master:
	2024-06-17  Peter Bergner  <bergner@linux.ibm.com>

	PR target/115389
	* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
	rop_hash_save_offset for non-Altivec compiles.

2024-07-22  Peter Bergner  <bergner@linux.ibm.com>

	Backported from master:
	2024-06-08  Peter Bergner  <bergner@linux.ibm.com>

	* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Update comment.

2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	Backported from master:
	2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	PR ipa/115033
	* ipa-modref.cc (modref_eaf_analysis::analyze_ssa_name): Fix checking of
	EAF flags when analysing values dereferenced as function parameters.

2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	Backported from master:
	2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	PR ipa/114207
	* ipa-prop.cc (unadjusted_ptr_and_unit_offset): Fix accounting of offsets in ADDR_EXPR.

2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	Backported from master:
	2024-07-22  Jan Hubicka  <hubicka@ucw.cz>

	PR ipa/115277
	* ipa-icf-gimple.cc (func_checker::compare_loops): compare loop
	bounds.

2024-07-22  Jan Hubicka  <jh@suse.cz>

	Backported from master:
	2024-05-14  Jan Hubicka  <jh@suse.cz>

	PR ipa/113291
	* ipa-inline.cc (enum can_inline_edge_by_limits_flags): New enum.
	(can_inline_edge_by_limits_p): Take flags instead of multiple bools; add flag
	for forcing inlinie limits.
	(can_early_inline_edge_p): Update.
	(want_inline_self_recursive_call_p): Update; use FORCE_LIMITS mode.
	(check_callers): Update.
	(update_caller_keys): Update.
	(update_callee_keys): Update.
	(recursive_inlining): Update.
	(add_new_edges_to_heap): Update.
	(speculation_useful_p): Update.
	(inline_small_functions): Clear DECL_DISREGARD_INLINE_LIMITS on self recursion.
	(flatten_function): Update.
	(inline_to_all_callers_1): Update.

2024-07-22  Maciej W. Rozycki  <macro@orcam.me.uk>

	Backported from master:
	2024-06-29  Maciej W. Rozycki  <macro@orcam.me.uk>

	PR rtl-optimization/115565
	* cse.cc (record_jump_cond): Use INT_MIN rather than -1 for
	`comparison_qty' if !REG_P.

2024-07-20  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/3931.md (vlbr, vstbr, vrepi): Remove.
	* config/s390/s390.md (xdee): Add FPRX2 mapping.
	* config/s390/vector.md (bhfgq): Add TF mapping.

2024-07-20  Siddhesh Poyarekar  <siddhesh@gotplt.org>

	Backported from master:
	2024-07-20  Siddhesh Poyarekar  <siddhesh@gotplt.org>

	* opt-suggestions.cc
	(option_proposer::build_option_suggestions): Pull OPTB
	definition out of the innermost loop.

2024-07-19  René Rebe  <rene@exactcode.de>

	Backported from master:
	2024-07-18  René Rebe  <rene@exactcode.de>
		    Peter Bergner  <bergner@linux.ibm.com>

	PR target/97367
	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Do not consider
	OPTION_MASK_ALTIVEC.
	(emit_asm_machine): For Altivec compiles, emit a ".machine altivec".

2024-07-19  Daniel Bertalan  <dani@danielbertalan.dev>

	Backported from master:
	2024-07-12  Daniel Bertalan  <dani@danielbertalan.dev>

	* value-pointer-equiv.cc: Change NULL to nullptr.

2024-07-19  Robin Dapp  <rdapp@ventanamicro.com>

	Backported from master:
	2024-05-31  Robin Dapp  <rdapp@ventanamicro.com>

	* config/riscv/vector.md: Split vwadd.wx/vwsub.wx pattern and
	add extended_scalar patterns.

2024-07-19  Robin Dapp  <rdapp@ventanamicro.com>

	Backported from master:
	2024-05-31  Robin Dapp  <rdapp@ventanamicro.com>

	PR target/115068
	* config/riscv/vector.md:  Split vfw<insn>.wf pattern.

2024-07-19  Fangrui Song  <maskray@gcc.gnu.org>

	Backported from master:
	2024-04-27  Fangrui Song  <maskray@gcc.gnu.org>

	* config/riscv/elf.h (LINK_SPEC): Add -X.
	* config/riscv/freebsd.h (LINK_SPEC): Add -X.
	* config/riscv/linux.h (LINK_SPEC): Add -X.

2024-07-19  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-04-29  Christoph Müllner  <christoph.muellner@vrull.eu>

	* common/config/riscv/riscv-common.cc: Move ziccamoa, ziccif,
	zicclsm, and ziccrse into riscv_zi_subext.
	* config/riscv/riscv.opt: Define MASK_ZIC64B for
	riscv_ziccmo_subext.

2024-07-19  Pan Li  <pan2.li@intel.com>

	Backported from master:
	2024-05-13  Pan Li  <pan2.li@intel.com>

	PR target/114988
	* config/riscv/riscv-vector-builtins.cc
	(validate_instance_type_required_extensions): New func impl to
	validate the intrinisc func type ops.
	(expand_builtin): Validate instance type before expand.

2024-07-19  Liao Shihua  <shihua@iscas.ac.cn>

	Backported from master:
	2024-05-27  Liao Shihua  <shihua@iscas.ac.cn>

	* config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.

2024-07-19  Pan Li  <pan2.li@intel.com>

	Backported from master:
	2024-06-14  Pan Li  <pan2.li@intel.com>

	PR target/115456
	* config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
	which contains the VF_ZVFHMIN for alignment.

2024-07-19  Pan Li  <pan2.li@intel.com>

	Backported from master:
	2024-06-13  Pan Li  <pan2.li@intel.com>

	PR target/115456
	* config/riscv/autovec.md: Take ZVFH mode iterator instead of
	the ZVFHMIN for the alignment.
	* config/riscv/vector-iterators.md: Add 2 new iterator
	V_VLS_ZVFH and VLS_ZVFH.

2024-07-19  Artemiy Volkov  <Artemiy.Volkov@synopsys.com>

	Backported from master:
	2024-06-23  Artemiy Volkov  <Artemiy.Volkov@synopsys.com>

	* config/riscv/riscv.cc (riscv_expand_conditional_move): Add a
	CONST0_RTX check.

2024-07-19  Robin Dapp  <rdapp@ventanamicro.com>

	Backported from master:
	2024-07-05  Robin Dapp  <rdapp@ventanamicro.com>

	* config/riscv/autovec.md: Add TU policy.
	* config/riscv/riscv-protos.h (enum insn_type): Define
	SCALAR_MOVE_MERGED_OP_TU.

2024-07-19  Fei Gao  <gaofei@eswincomputing.com>

	Backported from master:
	2024-07-08  Fei Gao  <gaofei@eswincomputing.com>

	* common/config/riscv/riscv-common.cc (riscv_subset_list::riscv_subset_list):
	init m_subset_num to 0.
	(riscv_subset_list::add): increase m_subset_num once a subset added.
	(riscv_subset_list::finalize): call handle_implied_ext repeatly
	until no change in m_subset_num.
	* config/riscv/riscv-subset.h: add m_subset_num member.

2024-07-18  Marek Polacek  <polacek@redhat.com>

	Backported from master:
	2024-07-18  Marek Polacek  <polacek@redhat.com>
		    Jakub Jelinek   <jakub@redhat.com>

	PR c++/115865
	* tree-eh.cc (get_eh_else): Check that the result of
	gimple_seq_first_stmt is non-null.

2024-07-18  LIU Hao  <lh_mouse@126.com>

	Backported from master:
	2024-07-18  LIU Hao  <lh_mouse@126.com>

	PR rtl-optimization/115049
	* varasm.cc (decl_binds_to_current_def_p): Add a check for COMDAT
	declarations too, like weak ones.

2024-07-18  Roger Sayle  <roger@nextmovesoftware.com>

	Backported from master:
	2024-06-07  Roger Sayle  <roger@nextmovesoftware.com>

	PR target/115351
	* config/i386/i386.cc (ix86_rtx_costs): Provide estimates for
	the *concatditi3 and *insvti_highpart patterns, about two insns.

2024-07-18  Jan Hubicka  <jh@suse.cz>

	Backported from master:
	2024-05-16  Jan Hubicka  <jh@suse.cz>

	PR ipa/113787
	* ipa-fnsummary.cc (points_to_local_or_readonly_memory_p): Do not
	look into TARGET_MEM_REFS with constant opreand 0.

2024-07-18  Roger Sayle  <roger@nextmovesoftware.com>

	Backported from master:
	2024-06-24  Roger Sayle  <roger@nextmovesoftware.com>
		    Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113673
	* gimple-ssa-store-merging.cc (find_bswap_or_nop_load): Make static.
	(find_bswap_or_nop_1): Avoid transformations (load merging) when
	stmt_can_throw_internal indicates that a statement can trap.

2024-07-17  Uros Bizjak  <ubizjak@gmail.com>

	Backported from master:
	2024-07-17  Uros Bizjak  <ubizjak@gmail.com>

	PR target/115526
	* config/alpha/alpha.md (movdi_er_high_g): Add cannot_copy attribute.
	(movdi_er_tlsgd): Ditto.
	(movdi_er_tlsldm): Ditto.
	(call_value_osf_<tls>): Ditto.

2024-07-17  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-07-17  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/115887
	* gimple-lower-bitint.cc (gimple_lower_bitint): Use gsi_insert_on_edge
	instead of gsi_insert_on_edge_immediate and set edge_insertions to
	true.

2024-07-17  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-07-17  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/115527
	* gimple-fold.cc (clear_padding_flush): Introduce endsize
	variable and use it instead of wordsize when comparing it against
	nonzero_last.
	(clear_padding_type): Increment off by sz.

2024-07-17  Robin Dapp  <rdapp@ventanamicro.com>

	Backported from master:
	2024-06-11  Robin Dapp  <rdapp@ventanamicro.com>

	PR tree-optimization/115382
	* tree-vect-loop.cc (vectorize_fold_left_reduction): Use
	prepare_vec_mask.
	* tree-vect-stmts.cc (check_load_store_for_partial_vectors):
	Remove static of prepare_vec_mask.
	* tree-vectorizer.h (prepare_vec_mask): Export.

2024-07-17  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115868
	* tree-vect-stmts.cc (vectorizable_simd_clone_call): Correctly
	compute the number of mask copies required for vect_record_loop_mask.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115841
	* tree-vect-loop.cc (vect_transform_cycle_phi): Correctly
	place the partial vector reduction for the accumulator
	re-use when the main loop cannot be skipped but the
	epilogue can.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115843
	* tree-vect-loop-manip.cc
	(vect_set_loop_condition_partial_vectors_avx512): Properly
	bias the shift of the initial mask for alignment peeling.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-06-30  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115701
	* tree-ssanames.cc (maybe_duplicate_ssa_info_at_copy):
	Only copy info from within the same BB.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-06-30  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115701
	* tree-ssanames.h (maybe_duplicate_ssa_info_at_copy): Declare.
	* tree-ssanames.cc (maybe_duplicate_ssa_info_at_copy): New
	function, split out from ...
	* tree-ssa-copy.cc (fini_copy_prop): ... here.
	* tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt): ...
	and here.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115867
	* tree-vect-stmts.cc (vectorizable_simd_clone_call): Properly
	guess the number of mask elements for integer mode masks.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-16  Richard Biener  <rguenther@suse.de>

	* config/i386/x86-tune-costs.h (znver5_cost): Update unaligned
	load and store cost from the aligned costs.

2024-07-16  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115843
	* config/i386/x86-tune-costs.h (znver4_cost): Update unaligned
	load and store cost from the aligned costs.

2024-07-16  Alexandre Oliva  <oliva@adacore.com>

	Backported from master:
	2024-07-12  Alexandre Oliva  <oliva@adacore.com>

	PR target/115459
	* config/alpha/alpha.cc (alpha_expand_block_move): Adjust
	MEMs to match inferred alignment.

2024-07-16  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-07-15  Christoph Müllner  <christoph.muellner@vrull.eu>

	* common/config/riscv/riscv-common.cc (riscv_subset_list::add):
	Allow adding enabled extension if m_allow_adding_dup is set.
	* config/riscv/riscv-subset.h: Add m_allow_adding_dup and setter.
	* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
	Allow adding enabled extensions.

2024-07-16  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-07-15  Christoph Müllner  <christoph.muellner@vrull.eu>

	PR target/115554
	PR target/115562
	* common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
	Remove.
	(struct riscv_func_target_hasher): Likewise.
	(riscv_func_decl_hash): Likewise.
	(riscv_func_target_hasher::hash): Likewise.
	(riscv_func_target_hasher::equal): Likewise.
	(riscv_current_subset_list): Likewise.
	(riscv_cmdline_subset_list): Remove obsolete space.
	(riscv_func_target_table_lazy_init): Remove.
	(riscv_func_target_get): Likewise.
	(riscv_func_target_put): Likewise.
	(riscv_func_target_remove_and_destory): Likewise.
	(riscv_arch_str): Generate from cmdline_subset_list.
	(riscv_set_arch_by_subset_list): Don't set current_subset_list.
	(riscv_parse_arch_string): Remove current_subset_list.
	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	Get subset list via riscv_cmdline_subset_list().
	* config/riscv/riscv-subset.h (riscv_current_subset_list):
	Remove prototype.
	(riscv_func_target_get): Likewise.
	(riscv_func_target_put): Likewise.
	(riscv_func_target_remove_and_destory): Likewise.
	* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
	Build base arch string from existing target options, if any.
	(riscv_target_attr_parser::update_settings): Store new arch
	string in target options.
	(riscv_process_one_target_attr): Whitespace fix.
	(riscv_process_target_attr): Drop opts argument.
	(riscv_option_valid_attribute_p): Properly save, change and restore
	target options.
	* config/riscv/riscv.cc (get_arch_str): New function.
	(riscv_declare_function_name): Get arch string for option-arch
	directive from function's target options.
	* config/riscv/riscv.opt: Add riscv_arch_string variable to
	march option.

2024-07-16  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-07-09  Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/riscv-target-attr.cc (riscv_process_target_attr):
	Fix comments and variable names.

2024-07-16  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-07-09  Christoph Müllner  <christoph.muellner@vrull.eu>

	* common/config/riscv/riscv-common.cc (riscv_set_arch_by_subset_list):
	Fix overlong line.
	(riscv_parse_arch_string): Replace duplicated code by a call to
	riscv_set_arch_by_subset_list.

2024-07-16  Alexandre Oliva  <oliva@adacore.com>

	Backported from master:
	2024-07-15  Alexandre Oliva  <oliva@adacore.com>

	PR target/113719
	* config/i386/i386-options.cc (ix86_option_override_internal):
	Move flag_omit_frame_pointer final overrider...
	(ix86_recompute_optlev_based_flags): ... here.

2024-07-16  Alexandre Oliva  <oliva@adacore.com>

	Backported from master:
	2024-07-03  Alexandre Oliva  <oliva@adacore.com>

	PR target/113719
	* config/i386/i386-options.cc
	(ix86_override_options_after_change_1): Add opts and opts_set
	parms, operate on them, after factoring out of...
	(ix86_override_options_after_change): ... this.  Restore calls
	of ix86_default_align and ix86_recompute_optlev_based_flags.
	(ix86_option_override_internal): Call the factored-out bits.

2024-07-16  H.J. Lu  <hjl.tools@gmail.com>

	Backported from master:
	2024-07-08  H.J. Lu  <hjl.tools@gmail.com>

	* config/i386/i386.cc (ix86_print_operand): Always generate
	branch hint for conditional branches.
	* config/i386/i386.h (TARGET_BRANCH_PREDICTION_HINTS): Split
	into ..
	(TARGET_BRANCH_PREDICTION_HINTS_TAKEN): .. this, and ..
	(TARGET_BRANCH_PREDICTION_HINTS_NOT_TAKEN): .. this.
	* config/i386/x86-tune.def (X86_TUNE_BRANCH_PREDICTION_HINTS):
	Split into ..
	(X86_TUNE_BRANCH_PREDICTION_HINTS_TAKEN): .. this, and ..
	(X86_TUNE_BRANCH_PREDICTION_HINTS_NOT_TAKEN): .. this.

2024-07-15  liuhongt  <hongtao.liu@intel.com>

	Backported from master:
	2024-07-15  liuhongt  <hongtao.liu@intel.com>

	PR target/115872
	* tree-ssa-ccp.cc (convert_atomic_bit_not): Remove use_stmt after use_nop_stmt is removed.
	(optimize_atomic_bit_test_and): Ditto.

2024-07-13  Lulu Cheng  <chenglulu@loongson.cn>

	Backported from master:
	2024-07-12  Lulu Cheng  <chenglulu@loongson.cn>

	PR target/115752
	* config/loongarch/loongarch.cc
	(loongarch_hard_regno_mode_ok_uncached): Replace
	UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
	* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.

2024-07-13  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	Backported from master:
	2024-07-12  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/vector.md (mov<mode>): Fix output template for
	movv1qi.

2024-07-13  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	Backported from master:
	2024-07-12  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>

	* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
	i.e., any constant integer between 0 and 15 for CC comparisons.

2024-07-12  YunQiang Su  <yunqiang@isrc.iscas.ac.cn>

	Backported from master:
	2024-07-12  YunQiang Su  <yunqiang@isrc.iscas.ac.cn>

	PR target/115840
	* config/riscv/riscv.cc(riscv_preferred_else_value): Mark
	tmp_var as NO_WARNING.

2024-07-11  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	Backported from master:
	2024-07-11  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/115611
	* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input
	scalar register pair when lane = 1.

2024-07-10  Uros Bizjak  <ubizjak@gmail.com>

	Backported from master:
	2024-07-10  Uros Bizjak  <ubizjak@gmail.com>

	PR middle-end/115836
	* expmed.cc (emit_store_flag_1): Move calculation of
	scode just before its only usage site.

2024-07-10  Fei Gao  <gaofei@eswincomputing.com>

	PR target/113715
	* config/riscv/riscv.cc (riscv_zcmp_can_use_popretz): Removed.
	(riscv_gen_multi_pop_insn): Remove generation of cm.popretz.

2024-07-09  Alfie Richards  <alfie.richards@arm.com>

	Backported from master:
	2024-07-04  Alfie Richards  <alfie.richards@arm.com>

	PR target/114890
	* config/aarch64/aarch64-simd.md: Remove bigendian operand swap.

2024-07-09  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	Backported from master:
	2024-07-05  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	PR target/115153
	* config/arm/arm.cc (arm_legitimate_index_p): Move LDRD case before
	NEON.
	(thumb2_legitimate_index_p): Update comments.
	(output_move_neon): Use DFmode for vldr/vstr and non-checking
	adjust_address.

2024-07-09  Haochen Jiang  <haochen.jiang@intel.com>

	* common/config/i386/cpuinfo.h (get_available_features): Correct
	AVX10 CPUID emulation to specify ecx value.

2024-07-09  Pan Li  <pan2.li@intel.com>

	Backported from master:
	2024-07-03  Pan Li  <pan2.li@intel.com>

	PR target/115763
	* config/riscv/vector.md (*pred_broadcast<mode>): Split into
	zvfh and zvfhmin part.
	(*pred_broadcast<mode>_zvfh): New define_insn for zvfh part.
	(*pred_broadcast<mode>_zvfhmin): Ditto but for zvfhmin.

2024-07-08  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-01  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115723
	* tree-vect-loop.cc (check_reduction_path): For a .COND_ADD
	verify the else value also refers to the reduction chain op.

2024-07-08  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-07-01  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115694
	* tree-ssa-forwprop.cc (pass_forwprop::execute): Check the
	store is complex before rewriting it.

2024-07-08  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-06-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115669
	* tree-vect-slp.cc (vect_build_slp_tree_2): Do not reassociate
	chains that participate in a reduction.

2024-07-08  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-06-26  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115646
	* tree-call-cdce.cc (check_pow): Check for bit_sz values
	as allowed by transform.

2024-07-08  Pali Rohár  <pali@kernel.org>

	Backported from master:
	2024-06-24  Pali Rohár  <pali@kernel.org>

	* config/i386/mingw-w64.h (CPP_SPEC): Add missing -mcrtdll=
	cases: msvcr40*, msvcrtd*.
	* config/i386/mingw32.h (CPP_SPEC): Add missing -mcrtdll=
	cases: msvcr40*, msvcrtd*.
	* doc/invoke.texi: Add missing -mcrtdll= cases: msvcr40*,
	msvcrtd*, msvcr71*. Express wildcards with *. Document _UCRT.

2024-07-06  Eric Botcazou  <ebotcazou@adacore.com>

	PR target/115591
	* config/riscv/riscv.cc (riscv_valid_lo_sum_p): Add missing test on
	tree_fits_uhwi_p before calling tree_to_uhwi.

2024-07-05  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	Backported from master:
	2024-07-02  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	PR target/115188
	* config/arm/arm.md (unaligned_loadsi): Use 'Uw' constraint and
	'mem_and_no_t1_wback_op'.
	(unaligned_loadhiu): Likewise.
	(unaligned_storesi): Likewise.
	(unaligned_storehi): Likewise.
	* config/arm/predicates.md (mem_and_no_t1_wback_op): Add new predicate.
	* config/arm/sync.md (arm_atomic_load<mode>): Use 'Uw' constraint.
	(arm_atomic_store<mode>): Likewise.

2024-07-05  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-07-05  Georg-Johann Lay  <avr@gjlay.de>

	PR target/87376
	* config/avr/avr-dimode.md: Use "nop_general_operand" instead
	of "general_operand" as predicate for all input operands.

2024-07-04  Kyrylo Tkachov  <ktkachov@nvidia.com>

	Backported from master:
	2024-07-03  Kyrylo Tkachov  <ktkachov@nvidia.com>

	PR target/115475
	* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
	Define __ARM_FEATURE_SVE_BF16 for TARGET_SVE_BF16.

2024-07-04  Kyrylo Tkachov  <ktkachov@nvidia.com>

	Backported from master:
	2024-07-03  Kyrylo Tkachov  <ktkachov@nvidia.com>

	PR target/115457
	* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
	Define __ARM_FEATURE_BF16 for TARGET_BF16_FP.

2024-07-03  John David Anglin  <danglin@gcc.gnu.org>

	Revert:
	2023-10-05  John David Anglin  <danglin@gcc.gnu.org>

	* config/pa/pa32-linux.h (MALLOC_ABI_ALIGNMENT): Delete.

2024-07-03  John David Anglin  <danglin@gcc.gnu.org>

	PR target/115691
	* config/pa/pa.md: Remove incorrect xmpyu patterns.

2024-07-03  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-07-03  Georg-Johann Lay  <avr@gjlay.de>

	PR target/98762
	* config/avr/avr.cc (avr_out_movqi_r_mr_reg_disp_tiny): Properly
	restore the base register when it is partially clobbered.

2024-07-03  Kewen Lin  <linkw@linux.ibm.com>

	Backported from master:
	2024-06-26  Kewen Lin  <linkw@linux.ibm.com>
		    Xionghu Luo  <xionghuluo@tencent.com>

	PR target/106069
	PR target/115355
	* config/rs6000/altivec.md (altivec_vmrghh_direct): Rename to ...
	(altivec_vmrghh_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
	(altivec_vmrghh_direct_le): New define_insn.
	(altivec_vmrglh_direct): Rename to ...
	(altivec_vmrglh_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
	(altivec_vmrglh_direct_le): New define_insn.
	(altivec_vmrghh): Adjust by calling gen_altivec_vmrghh_direct_be
	for BE and gen_altivec_vmrglh_direct_le for LE.
	(altivec_vmrglh): Adjust by calling gen_altivec_vmrglh_direct_be
	for BE and gen_altivec_vmrghh_direct_le for LE.
	(vec_widen_umult_hi_v16qi): Adjust the call to
	gen_altivec_vmrghh_direct by gen_altivec_vmrghh for BE
	and by gen_altivec_vmrglh for LE.
	(vec_widen_smult_hi_v16qi): Likewise.
	(vec_widen_umult_lo_v16qi): Adjust the call to
	gen_altivec_vmrglh_direct by gen_altivec_vmrglh for BE
	and by gen_altivec_vmrghh for LE.
	(vec_widen_smult_lo_v16qi): Likewise.
	* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
	CODE_FOR_altivec_vmrghh_direct by
	CODE_FOR_altivec_vmrghh_direct_be for BE and
	CODE_FOR_altivec_vmrghh_direct_le for LE.  And replace
	CODE_FOR_altivec_vmrglh_direct by
	CODE_FOR_altivec_vmrglh_direct_be for BE and
	CODE_FOR_altivec_vmrglh_direct_le for LE.

2024-07-03  Kewen Lin  <linkw@linux.ibm.com>

	Backported from master:
	2024-06-26  Kewen Lin  <linkw@linux.ibm.com>
		    Xionghu Luo  <xionghuluo@tencent.com>

	PR target/106069
	PR target/115355
	* config/rs6000/altivec.md (altivec_vmrghb_direct): Rename to ...
	(altivec_vmrghb_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
	(altivec_vmrghb_direct_le): New define_insn.
	(altivec_vmrglb_direct): Rename to ...
	(altivec_vmrglb_direct_be): ... this.  Add condition BYTES_BIG_ENDIAN.
	(altivec_vmrglb_direct_le): New define_insn.
	(altivec_vmrghb): Adjust by calling gen_altivec_vmrghb_direct_be
	for BE and gen_altivec_vmrglb_direct_le for LE.
	(altivec_vmrglb): Adjust by calling gen_altivec_vmrglb_direct_be
	for BE and gen_altivec_vmrghb_direct_le for LE.
	* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
	CODE_FOR_altivec_vmrghb_direct by
	CODE_FOR_altivec_vmrghb_direct_be for BE and
	CODE_FOR_altivec_vmrghb_direct_le for LE.  And replace
	CODE_FOR_altivec_vmrglb_direct by
	CODE_FOR_altivec_vmrglb_direct_be for BE and
	CODE_FOR_altivec_vmrglb_direct_le for LE.

2024-07-02  Alex Coplan  <alex.coplan@arm.com>

	Backported from master:
	2024-05-08  Alex Coplan  <alex.coplan@arm.com>

	PR target/114936
	* config/aarch64/aarch64-ldp-fusion.cc (combine_reg_notes):
	Ensure insn iN has its REG_FRAME_RELATED_EXPR (if any) stored in
	FR_EXPR[N-1], thus matching the correspondence expected by the
	copy_rtx calls.

2024-07-01  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-07-01  Georg-Johann Lay  <avr@gjlay.de>

	PR target/88236
	PR target/115726
	* config/avr/avr.md (mov<mode>) [avr_mem_memx_p]: Expand in such a
	way that the destination does not overlap with any hard register
	clobbered / used by xload8qi_A resp. xload<mode>_A.
	* config/avr/avr.cc (avr_out_xload): Avoid early-clobber
	situation for Z by executing just one load when the output register
	overlaps with Z.

2024-06-28  Kewen Lin  <linkw@linux.ibm.com>

	Backported from master:
	2024-06-21  Kewen Lin  <linkw@linux.ibm.com>
		    Xionghu Luo  <xionghuluo@tencent.com>

	PR target/106069
	PR target/115355
	* config/rs6000/altivec.md (altivec_vmrghw_direct_<VSX_W:mode>): Rename
	to ...
	(altivec_vmrghw_direct_<VSX_W:mode>_be): ... this.  Add the condition
	BYTES_BIG_ENDIAN.
	(altivec_vmrghw_direct_<VSX_W:mode>_le): New define_insn.
	(altivec_vmrglw_direct_<VSX_W:mode>): Rename to ...
	(altivec_vmrglw_direct_<VSX_W:mode>_be): ... this.  Add the condition
	BYTES_BIG_ENDIAN.
	(altivec_vmrglw_direct_<VSX_W:mode>_le): New define_insn.
	(altivec_vmrghw): Adjust by calling gen_altivec_vmrghw_direct_v4si_be
	for BE and gen_altivec_vmrglw_direct_v4si_le for LE.
	(altivec_vmrglw): Adjust by calling gen_altivec_vmrglw_direct_v4si_be
	for BE and gen_altivec_vmrghw_direct_v4si_le for LE.
	(vec_widen_umult_hi_v8hi): Adjust the call to
	gen_altivec_vmrghw_direct_v4si by gen_altivec_vmrghw for BE
	and by gen_altivec_vmrglw for LE.
	(vec_widen_smult_hi_v8hi): Likewise.
	(vec_widen_umult_lo_v8hi): Adjust the call to
	gen_altivec_vmrglw_direct_v4si by gen_altivec_vmrglw for BE
	and by gen_altivec_vmrghw for LE
	(vec_widen_smult_lo_v8hi): Likewise.
	* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
	CODE_FOR_altivec_vmrghw_direct_v4si by
	CODE_FOR_altivec_vmrghw_direct_v4si_be for BE and
	CODE_FOR_altivec_vmrghw_direct_v4si_le for LE.  And replace
	CODE_FOR_altivec_vmrglw_direct_v4si by
	CODE_FOR_altivec_vmrglw_direct_v4si_be for BE and
	CODE_FOR_altivec_vmrglw_direct_v4si_le for LE.
	* config/rs6000/vsx.md (vsx_xxmrghw_<VSX_W:mode>): Adjust by calling
	gen_altivec_vmrghw_direct_v4si_be for BE and
	gen_altivec_vmrglw_direct_v4si_le for LE.
	(vsx_xxmrglw_<VSX_W:mode>): Adjust by calling
	gen_altivec_vmrglw_direct_v4si_be for BE and
	gen_altivec_vmrghw_direct_v4si_le for LE.

2024-06-27  Kyrylo Tkachov  <ktkachov@nvidia.com>

	* config/aarch64/aarch64-cores.def (grace): New entry.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* doc/invoke.texi (AArch64 Options): Document the above.

2024-06-27  Jiawei  <jiawei@iscas.ac.cn>

	* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New conditions.

2024-06-25  Eric Botcazou  <ebotcazou@adacore.com>

	PR target/115608
	* config/sparc/linux64.h (CC1_SPEC): Pass -m32 for -mv8plus.

2024-06-24  Kewen Lin  <linkw@linux.ibm.com>

	Backported from master:
	2024-05-29  Kewen Lin  <linkw@linux.ibm.com>

	PR target/114846
	* config/rs6000/rs6000-logue.cc (rs6000_emit_epilogue): As
	EPILOGUE_TYPE_EH_RETURN would be passed as epilogue_type directly
	now, adjust the relevant handlings on it.
	* config/rs6000/rs6000.md (eh_return expander): Append by calling
	gen_eh_return_internal and emit_barrier.
	(eh_return_internal): New define_insn_and_split, call function
	rs6000_emit_epilogue with epilogue type EPILOGUE_TYPE_EH_RETURN.

2024-06-21  YunQiang Su  <syq@gcc.gnu.org>

	Backported from master:
	2024-06-21  YunQiang Su  <syq@gcc.gnu.org>

	* configure.ac: Set gcc_cv_as_mips_explicit_relocs if
	gcc_cv_as_mips_explicit_relocs_pcrel.
	* configure: Regenerate.

2024-06-21  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-31  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115278
	* tree-if-conv.cc (ifcvt_local_dce): Do not DSE volatile stores.

2024-06-21  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-06-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115508
	* tree-vect-slp.cc (vect_schedule_slp_node): Guard check on
	representative.

2024-06-21  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-22  Richard Biener  <rguenther@suse.de>

	* tree-vect-slp.cc (vect_schedule_slp_node): Avoid looking
	at SLP_REPRESENTATIVE for VEC_PERM nodes.

2024-06-20  Andreas Krebbel  <krebbel@linux.ibm.com>

	Backported from master:
	2024-06-10  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/s390/s390.cc (expand_perm_as_replicate): Handle memory
	operands.
	* config/s390/vx-builtins.md (vec_splats<mode>): Turn into parameterized expander.
	(@vec_splats<mode>): New expander.

2024-06-20  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-19  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/115544
	* gimple-lower-bitint.cc (gimple_lower_bitint): Disable optimizing
	loads used by COMPLEX_EXPR operands.

2024-06-20  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-17  Jakub Jelinek  <jakub@redhat.com>

	PR driver/115440
	* opts-common.cc (add_misspelling_candidates): If opt1 is non-NULL,
	add a space and opt1 to the alternative suggestion text.

2024-06-17  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	Backported from master:
	2024-05-23  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	PR target/109549
	* config/s390/s390.cc (TARGET_NOCE_CONVERSION_PROFITABLE_P):
	Define.
	(s390_noce_conversion_profitable_p): Implement.

2024-06-15  Christoph Müllner  <christoph.muellner@vrull.eu>

	Backported from master:
	2024-06-15  Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
	Fix allocation size of buffer.
	(riscv_process_one_target_attr): Likewise.
	(riscv_process_target_attr): Likewise.

2024-06-12  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>

	Backported from master:
	2024-06-12  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
		    Yvan ROUX  <yvan.roux@foss.st.com>

	PR target/115253
	* config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear):
	Sign extend for Thumb1.
	(thumb1_expand_prologue): Add zero/sign extend.

2024-06-11  Richard Sandiford  <richard.sandiford@arm.com>

	Backported from master:
	2024-05-30  Richard Sandiford  <richard.sandiford@arm.com>

	PR rtl-optimization/115281
	* ira-conflicts.cc (go_through_subreg): Use the natural size of
	the inner mode rather than the outer mode.

2024-06-07  Richard Ball  <richard.ball@arm.com>

	Backported from master:
	2024-06-06  Richard Ball  <richard.ball@arm.com>

	PR target/115353
	* config/arm/arm.h (enum arm_auto_incmodes):
	Correct CASE_VECTOR_SHORTEN_MODE query.

2024-06-07  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-07  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/115352
	* gimple-lower-bitint.cc (lower_addsub_overflow): Don't disable
	single_comparison if cmp_code is GE_EXPR.

2024-06-06  Richard Ball  <richard.ball@arm.com>

	Backported from master:
	2024-06-06  Richard Ball  <richard.ball@arm.com>

	* config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
	Add missing __ARM_NEON_SVE_BRIDGE.

2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/115337
	* fold-const.cc (tree_call_nonnegative_warnv_p) <CASE_CFN_CLZ>:
	If arg1 is non-NULL, RECURSE on it, otherwise return true.

2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/108789
	* builtins.cc (fold_builtin_arith_overflow): For ovf_only,
	don't call save_expr and don't build REALPART_EXPR, otherwise
	set TREE_SIDE_EFFECTS on call before calling save_expr.
	(fold_builtin_addc_subc): Set TREE_SIDE_EFFECTS on call before
	calling save_expr.

2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	* doc/invoke.texi (lujiazui): Clarify that while the CPUs do support
	AVX and F16C, -march=lujiazui actually doesn't enable those.

2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-06-03  Jakub Jelinek  <jakub@redhat.com>

	PR target/115324
	* config/rs6000/rs6000-gen-builtins.cc (write_decls): Remove
	GTY markup from struct bifdata and struct ovlddata and remove their
	fntype members.  Change next member in struct ovlddata and
	first_instance member of struct ovldrecord to have int type rather
	than struct ovlddata *.  Remove GTY markup from rs6000_builtin_info
	and rs6000_instance_info arrays, declare new
	rs6000_builtin_info_fntype and rs6000_instance_info_fntype arrays,
	which have GTY markup.
	(write_bif_static_init): Adjust for the above changes.
	(write_ovld_static_init): Likewise.
	(write_init_bif_table): Likewise.
	(write_init_ovld_table): Likewise.
	* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Likewise.
	* config/rs6000/rs6000-c.cc (find_instance): Likewise.  Make static.
	(altivec_resolve_overloaded_builtin): Adjust for the above changes.

2024-06-04  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-15  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/114902
	PR rtl-optimization/115092
	* combine.cc (simplify_compare_const): Don't optimize
	GE op0 SIGNED_MIN or LT op0 SIGNED_MIN into NE op0 const0_rtx or
	EQ op0 const0_rtx.

2024-06-03  Haochen Jiang  <haochen.jiang@intel.com>

	* common/config/i386/i386-common.cc: Change Granite Rapids
	series CPU type to P_PROC_AVX10_1_512.
	* common/config/i386/i386-cpuinfo.h (enum feature_priority):
	Revise comment part. Add P_AVX10_1_256, P_AVX10_1_512,
	P_PROC_AVX10_1_512.
	* common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512.

2024-06-01  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-06-01  Georg-Johann Lay  <avr@gjlay.de>

	PR tree-optimization/115307
	* config/avr/avr.md (SFDF): New mode iterator.
	(isinf<mode>2) [sf, df]: New expanders.

2024-05-31  Uros Bizjak  <ubizjak@gmail.com>

	Backported from master:
	2024-05-31  Uros Bizjak  <ubizjak@gmail.com>

	PR target/115297
	* config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
	operands 3 and 4 with truncate:SI RTX.
	(*divmodsi_internal_er): Ditto for operands 1 and 2.
	(*divmodsi_internal_er_1): Ditto.
	(*divmodsi_internal): Ditto.
	* config/alpha/constraints.md ("b"): Correct register
	number in the description.

2024-05-31  Richard Sandiford  <richard.sandiford@arm.com>

	Backported from master:
	2024-05-24  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/115192
	* tree-data-ref.cc (create_intersect_range_checks): Take the
	alignment of the access sizes into account.

2024-05-31  Hongyu Wang  <hongyu.wang@intel.com>

	Backported from master:
	2024-05-29  Hongyu Wang  <hongyu.wang@intel.com>

	PR target/113719
	* config/i386/i386-options.cc (ix86_override_options_after_change):
	Remove call to ix86_default_align and
	ix86_recompute_optlev_based_flags.
	(ix86_option_override_internal): Call ix86_default_align and
	ix86_recompute_optlev_based_flags.

2024-05-30  YunQiang Su  <syq@gcc.gnu.org>

	Backported from master:
	2024-05-29  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.cc(mips16_gp_pseudo_reg): Mark
	MIPS16_PIC_TEMP and MIPS_PROLOGUE_TEMP clobbered.
	(mips_emit_call_insn): Mark MIPS16_PIC_TEMP and
	MIPS_PROLOGUE_TEMP clobbered if MIPS16 and CALL_CLOBBERED_GP.

2024-05-29  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115149
	* tree-ssa-live.cc (virtual_operand_live::get_live_in):
	Explicitly track the first processed edge.

2024-05-29  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-23  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115197
	* tree-loop-distribution.cc (copy_loop_before): Constant PHI
	args remain the same.

2024-05-29  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-07  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114921
	* tree-vect-stmts.cc (vectorizable_assignment): Use
	tree_nop_conversion_p to identify converts we can vectorize
	with a simple assignment.

2024-05-29  liuhongt  <hongtao.liu@intel.com>

	* config/i386/i386.cc (ix86_avoid_jump_mispredicts): Change
	gen_pad to gen_max_skip_align.
	(ix86_align_loops): New function.
	(ix86_reorg): Call ix86_align_loops.
	* config/i386/i386.md (pad): Rename to ..
	(max_skip_align): .. this, and accept 2 operands for align and
	skip.

2024-05-29  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/x86-tune-costs.h (generic_cost): Change from
	16:11:8 to 16.

2024-05-28  Xi Ruoyao  <xry111@xry111.site>

	Backported from master:
	2024-05-28  Xi Ruoyao  <xry111@xry111.site>

	PR target/115169
	* config/loongarch/loongarch.cc
	(loongarch_expand_conditional_move): Guard REGNO with REG_P.

2024-05-27  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115232
	* gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
	failure to demangle gracefully.

2024-05-23  Martin Jambor  <mjambor@suse.cz>

	Backported from master:
	2024-05-09  Martin Jambor  <mjambor@suse.cz>

	* tree-sra.cc (sra_modify_assign): Remove the original statement
	also when dealing with a store to a fully covered aggregate from a
	non-candidate.

2024-05-22  Eric Botcazou  <ebotcazou@adacore.com>

	PR rtl-optimization/115038
	* fold-mem-offsets.cc (fold_offsets): Return 0 if the defining
	instruction of the register is frame related.

2024-05-22  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-22  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/115152
	* tree-ssa-strlen.cc (strlen_pass::count_nonzero_bytes_addr): If
	!si->full_string_p, clear *nulterm and set maxlen to nbytes.

2024-05-22  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-22  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/115172
	* ubsan.cc (instrument_bool_enum_load): If rhs is not in generic
	address space, use qualified version of utype with the right
	address space.  Formatting fix.

2024-05-22  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/115069
	* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
	Do not enable the optimization when AVX512BW is not enabled.

2024-05-21  Andrew Pinski  <quic_apinski@quicinc.com>

	Backported from master:
	2024-05-21  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/115154
	* match.pd (convert (mult zero_one_valued_p@1 INTEGER_CST@2)): Disable
	for 1bit signed types.

2024-05-20  Andrew Pinski  <quic_apinski@quicinc.com>

	Backported from master:
	2024-05-20  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/115143
	* tree-ssa-phiopt.cc (minmax_replacement): Check for empty
	phi nodes for middle bbs for the case where middle bb is not empty.

2024-05-17  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-10  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114998
	* tree-loop-distribution.cc (free_rdg): Take loop argument.
	Reset UIDs of stmts still in the IL rather than all stmts
	referenced from the RDG.
	(loop_distribution::build_rdg): Pass loop to free_rdg.
	(loop_distribution::distribute_loop): Likewise.
	(loop_distribution::transform_reduction_loop): Likewise.

2024-05-15  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-07  Richard Biener  <rguenther@suse.de>

	PR middle-end/114931
	* tree.cc (type_hash_canon_hash): Hash TYPE_STRUCTURAL_EQUALITY_P.
	(type_cache_hasher::equal): Compare TYPE_STRUCTURAL_EQUALITY_P.
	(build_array_type_1): Set TYPE_STRUCTURAL_EQUALITY_P before
	probing with type_hash_canon.
	(build_function_type): Likewise.
	(build_method_type_directly): Likewise.
	(build_offset_type): Likewise.
	(build_complex_type): Likewise.
	* attribs.cc (build_type_attribute_qual_variant): Likewise.

2024-05-15  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-03  Richard Biener  <rguenther@suse.de>

	PR middle-end/114931
	* tree.cc (build_array_type_1): Return early when type_hash_canon
	returned an older existing type.
	(build_function_type): Likewise.
	(build_method_type_directly): Likewise.
	(build_offset_type): Likewise.

2024-05-12  Gerald Pfeifer  <gerald@pfeifer.com>

	Backported from master:
	2024-05-01  Gerald Pfeifer  <gerald@pfeifer.com>

	PR target/69374
	PR target/112959
	* doc/install.texi (Specific) <*-*-freebsd*>: The Ada and D
	run-time libraries are broken on i386 which also can affect
	64-bit builds. Go is broken.

2024-05-12  Gerald Pfeifer  <gerald@pfeifer.com>

	Backported from master:
	2024-05-01  Gerald Pfeifer  <gerald@pfeifer.com>

	PR target/69374
	PR target/112959
	* doc/install.texi (Specific) <*-*-freebsd*>: No longer refer
	to GCC or binutils in base. Recommend bootstrap using binutils.

2024-05-12  Gerald Pfeifer  <gerald@pfeifer.com>

	Backported from master:
	2024-05-01  Gerald Pfeifer  <gerald@pfeifer.com>

	PR target/69374
	* doc/install.texi (Specific) <ia64-*-hpux*>: Remove details
	on libunwind for GCC 3.4 and earlier.

2024-05-12  Gerald Pfeifer  <gerald@pfeifer.com>

	Backported from master:
	2024-04-28  Gerald Pfeifer  <gerald@pfeifer.com>

	PR target/69374
	PR target/112959
	* doc/install.texi (Specific) <*-*-freebsd*>: Remove references to
	FreeBSD 7 and older.

2024-05-10  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-10  Jakub Jelinek  <jakub@redhat.com>

	PR target/114968
	* target.def (use_atexit_for_cxa_atexit): Remove spurious space
	from comment.
	(adjust_cdtor_callabi_fntype): New cxx target hook.
	* targhooks.h (default_cxx_adjust_cdtor_callabi_fntype): Declare.
	* targhooks.cc (default_cxx_adjust_cdtor_callabi_fntype): New
	function.
	* doc/tm.texi.in (TARGET_CXX_ADJUST_CDTOR_CALLABI_FNTYPE): Add.
	* doc/tm.texi: Regenerate.
	* config/i386/i386.cc (ix86_cxx_adjust_cdtor_callabi_fntype): New
	function.
	(TARGET_CXX_ADJUST_CDTOR_CALLABI_FNTYPE): Redefine.

2024-05-10  Xi Ruoyao  <xry111@xry111.site>

	Backported from master:
	2024-05-10  Xi Ruoyao  <xry111@xry111.site>

	PR driver/114980
	* opts-common.cc (prune_options): Move -fdiagnostics-urls=
	early like -fdiagnostics-color=.

2024-05-09  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-05-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114975
	* config/avr/avr.md: Add combine pattern for
	8-bit parity detection.

2024-05-09  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-05-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114975
	* config/avr/avr.md: Add combine pattern for
	8-bit popcount detection.

2024-05-08  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114965
	* tree-ssa-reassoc.cc (optimize_range_tests_to_bit_test): Don't try to
	optimize away exp - lowi subtraction from shift count unless entry
	test is emitted or unless r.upper_bound () is smaller than prec.

2024-05-07  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-07  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114907
	* expr.cc (convert_mode_scalar): Use trunc_optab rather than
	sext_optab for HF->BF conversions.
	* optabs-libfuncs.cc (gen_trunc_conv_libfunc): Likewise.

2024-05-07  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-05-07  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/114956
	* tree-inline.cc: Include asan.h.
	(copy_bb): Remove also .ASAN_MARK calls if id->dst_fn has asan/hwasan
	sanitization disabled.

2024-05-07  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-04-30  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114876
	* gimple-ssa-sprintf.cc (format_character): For min == 0 && max == 0,
	set max, likely and unlikely members to 1 rather than 0.  Remove
	useless res.knownrange = true;.  Formatting fixes.

2024-05-07  Georg-Johann Lay  <avr@gjlay.de>

	Backported from master:
	2024-05-06  Georg-Johann Lay  <avr@gjlay.de>

	PR ipa/92606
	* config/avr/avr.cc (avr_option_override): Set
	flag_ipa_icf_variables = 0.

2024-05-07  Release Manager

	* GCC 14.1.0 released.

2024-05-03  Richard Biener  <rguenther@suse.de>

	Revert:
	2024-05-03  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114921
	* tree-vect-stmts.cc (vectorizable_assignment): Require
	same vector component modes for input and output for
	CONVERT_EXPR_CODE_P.

2024-05-03  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-04-30  Richard Biener  <rguenther@suse.de>

	PR middle-end/114734
	* internal-fn.cc (expand_call_mem_ref): Use
	get_gimple_for_ssa_name to get at the def stmt of the address
	argument to honor SSA coalescing constraints.

2024-05-03  Alex Coplan  <alex.coplan@arm.com>

	Backported from master:
	2024-05-03  Alex Coplan  <alex.coplan@arm.com>

	PR rtl-optimization/114924
	* cfgrtl.cc (duplicate_insn_chain): When updating MEM_EXPRs,
	don't strip (e.g.) ARRAY_REFs from the final MEM_EXPR.

2024-05-03  Richard Biener  <rguenther@suse.de>

	Backported from master:
	2024-05-03  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114921
	* tree-vect-stmts.cc (vectorizable_assignment): Require
	same vector component modes for input and output for
	CONVERT_EXPR_CODE_P.

2024-04-30  Jakub Jelinek  <jakub@redhat.com>

	Backported from master:
	2024-04-30  Jakub Jelinek  <jakub@redhat.com>
		    Hongtao Liu  <hongtao.liu@intel.com>

	PR tree-optimization/114883
	* tree-vect-loop.cc (vect_transform_reduction): Allow IFN_COND_MIN and
	IFN_COND_MAX in the assert.

2024-04-29  Pan Li  <pan2.li@intel.com>

	Backported from master:
	2024-04-29  Pan Li  <pan2.li@intel.com>

	PR target/114885
	* config/riscv/riscv.cc (riscv_legitimize_subreg_const_poly_move): New
	func impl to take care of (const_int_poly:TI 8).
	(riscv_legitimize_move): Handle subreg is const_int_poly,

2024-04-27  Xi Ruoyao  <xry111@xry111.site>

	Backported from master:
	2024-04-27  Xi Ruoyao  <xry111@xry111.site>

	PR target/114861
	* config/loongarch/loongarch.md (bstrins_<mode>_for_mask): Add
	constraints for operands.
	(bstrins_<mode>_for_ior_mask): Likewise.

2024-04-26  Frederik Harwath  <frederik@harwath.name>

	* config.gcc: Add gfx90c.
	* config/gcn/gcn-hsa.h (NO_SRAM_ECC): Likewise.
	* config/gcn/gcn-opts.h (enum processor_type): Likewise.
	(TARGET_GFX90c): New macro.
	* config/gcn/gcn.cc (gcn_option_override): Handle gfx90c.
	(gcn_omp_device_kind_arch_isa): Likewise.
	(output_file_start): Likewise.
	* config/gcn/gcn.h: Add gfx90c.
	* config/gcn/gcn.opt: Likewise.
	* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX90c): New macro.
	(get_arch): Handle gfx90c.
	(main): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c
	* config/gcn/t-omp-device: Add gfx90c.
	* doc/install.texi: Likewise.
	* doc/invoke.texi: Likewise.

2024-04-25  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf.h (PREFERRED_DEBUGGING_TYPE): Set to BTF_DEBUG.

2024-04-25  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf.cc (bpf_option_override): Improve handling of CO-RE
	options to avoid issues with -gtoggle.

2024-04-25  Jakub Jelinek  <jakub@redhat.com>

	PR fortran/114825
	* tree-nested.cc (get_debug_decl): New function.
	(get_nonlocal_debug_decl): Use it.
	(get_local_debug_decl): Likewise.

2024-04-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/bpf/bpf.opt: Use ASM_PSEUDOC for the default value of
	-masm.
	* config/bpf/bpf.h (ASM_SPEC): Adapt accordingly.
	* doc/invoke.texi (eBPF Options): Update.

2024-04-25  Richard Ball  <richard.ball@arm.com>

	PR target/114837
	* config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear):
	Add zero/sign extend.
	(arm_expand_prologue): Add zero/sign extend.

2024-04-25  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114792
	* tree-ssa-loop-ch.cc (ch_order_loops): New function.
	(ch_base::copy_headers): Sort loops to unloop inner-to-outer.

2024-04-25  Eric Botcazou  <ebotcazou@adacore.com>

	PR target/114416
	* config/sparc/sparc.h (SUN_V9_ABI_COMPATIBILITY): New macro.
	* config/sparc/sol2.h (SUN_V9_ABI_COMPATIBILITY): Redefine it.
	* config/sparc/sparc.cc (fp_type_for_abi): New predicate.
	(traverse_record_type): Use it to spot floating-point types.
	(compute_fp_layout): Also deal with array types.

2024-04-25  Pan Li  <pan2.li@intel.com>

	* config/riscv/vector-crypto.md: Add early clobber to the
	dest operand of vwsll.

2024-04-25  Haochen Gui  <guihaoc@gcc.gnu.org>

	* config/rs6000/altivec.md (*bcdinvalid_<mode>): Replace bcdadd
	with bcdsub.
	(bcdinvalid_<mode>): Likewise.

2024-04-24  Jakub Jelinek  <jakub@redhat.com>

	PR other/114738
	* opts.cc (get_option_url): Revert 2024-04-17 changes.
	* gcc-urlifier.cc: Don't include diagnostic-core.h.
	(gcc_urlifier::make_doc_url): Revert 2024-04-17 changes.
	* configure.ac (documentation-root-url): On release branches
	append gcc-MAJOR.MINOR.0/ to the default DOCUMENTATION_ROOT_URL.
	* doc/install.texi (--with-documentation-root-url=): Document
	the change of the default.
	* configure: Regenerate.

2024-04-24  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-11-29  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
		    kito-cheng  <kito.cheng@sifive.com>
		    kito-cheng  <kito.cheng@gmail.com>

	PR target/112431
	* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): New register filters.
	* config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Ditto.
	(no,yes): Ditto.
	* config/riscv/vector.md: Support highpart register overlap for vwcvt.

2024-04-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config.gcc: Add bpf-c.o as a target object for C and C++.
	* config/bpf/bpf.cc (bpf_target_macros): Move to bpf-c.cc.
	* config/bpf/bpf-c.cc: New file.
	(bpf_target_macros): Move from bpf.cc and define BPF CPU
	feature	macros.
	* config/bpf/t-bpf: Add rules to build bpf-c.o.

2024-04-24  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114787
	* tree-cfg.cc (remove_edge_and_dominated_blocks): When
	removing a loop backedge clear niter info and when removing
	the last backedge of a loop mark that loop for removal.

2024-04-24  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114832
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Fix dominance check.

2024-04-24  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
	Check whether AVX512F is explicitly enabled.

2024-04-24  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-11-30  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/vector.md: Support highpart overlap for vext.vf2

2024-04-23  Jakub Jelinek  <jakub@redhat.com>

	PR target/114810
	* config/i386/i386.md (*andn<dwi>3_doubleword_bmi): Split the =&r,r,ro
	alternative into =&r,r,r enabled only for x64 and =&r,r,o.

2024-04-23  Jan Hubicka  <jh@suse.cz>

	* doc/invoke.texi (-ftree-loop-distribute-patterns): Remove duplicated
	sentence about optimization flags implying this.

2024-04-23  Jakub Jelinek  <jakub@redhat.com>

	* config/darwin.opt (init): Spelling fix: initialiser -> initializer.

2024-04-23  Jakub Jelinek  <jakub@redhat.com>

	* config/epiphany/epiphany.opt (may-round-for-trunc): Spelling fix:
	floatig -> floating.
	* config/riscv/riscv.opt (mcsr-check): Spelling fix: CRS -> CSR.
	* params.opt (-param=ipa-cp-profile-count-base=): Spelling fix:
	frequncy -> frequency.

2024-04-23  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114799
	* tree-vect-slp.cc (vect_get_and_check_slp_defs): Properly
	update ->any_pattern when swapping operands.

2024-04-23  Andreas Krebbel  <krebbel@linux.ibm.com>

	PR target/114676
	* config/s390/s390-c.cc (s390_expand_overloaded_builtin): Use a
	MEM_REF with an addend of type ptr_type_node.

2024-04-23  Yang Yujie  <yangyujie@loongson.cn>

	* config.gcc: Add loongarch-evolution.o.
	* config/loongarch/genopts/genstr.sh: Enable generation of
	loongarch-evolution.[cc,h].
	* config/loongarch/t-loongarch: Likewise.
	* config/loongarch/genopts/gen-evolution.awk: New file.
	* config/loongarch/genopts/isa-evolution.in: Mark ISA version
	of introduction for each ISA evolution feature.
	* config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins):
	Define builtin macros for enabled ISA evolutions and the ISA
	version.
	* config/loongarch/loongarch-cpu.cc: Use loongarch-evolution.h.
	* config/loongarch/loongarch.h: Likewise.
	* config/loongarch/loongarch-cpucfg-map.h: Delete.
	* config/loongarch/loongarch-evolution.cc: New file.
	* config/loongarch/loongarch-evolution.h: New file.
	* config/loongarch/loongarch-opts.h (ISA_HAS_FRECIPE): Define.
	(ISA_HAS_DIV32): Likewise.
	(ISA_HAS_LAM_BH): Likewise.
	(ISA_HAS_LAMCAS): Likewise.
	(ISA_HAS_LD_SEQ_SA): Likewise.

2024-04-23  Yang Yujie  <yangyujie@loongson.cn>

	* config.gcc: Make la64v1.0 the default ISA preset of the lp64d ABI.
	* config/loongarch/genopts/loongarch-strings: Define la64v1.0, la64v1.1.
	* config/loongarch/genopts/loongarch.opt.in: Likewise.
	* config/loongarch/loongarch-c.cc (LARCH_CPP_SET_PROCESSOR): Likewise.
	(loongarch_cpu_cpp_builtins): Likewise.
	* config/loongarch/loongarch-cpu.cc (get_native_prid): Likewise.
	(fill_native_cpu_config): Likewise.
	* config/loongarch/loongarch-def.cc (array_tune): Likewise.
	* config/loongarch/loongarch-def.h: Likewise.
	* config/loongarch/loongarch-driver.cc (driver_set_m_parm): Likewise.
	(driver_get_normalized_m_opts): Likewise.
	* config/loongarch/loongarch-opts.cc (default_tune_for_arch): Likewise.
	(TUNE_FOR_ARCH): Likewise.
	(arch_str): Likewise.
	(loongarch_target_option_override): Likewise.
	* config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Likewise.
	(TARGET_uARCH_LA664): Likewise.
	* config/loongarch/loongarch-str.h (STR_CPU_ABI_DEFAULT): Likewise.
	(STR_ARCH_ABI_DEFAULT): Likewise.
	(STR_TUNE_GENERIC): Likewise.
	(STR_ARCH_LA64V1_0): Likewise.
	(STR_ARCH_LA64V1_1): Likewise.
	* config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width): Likewise.
	(loongarch_asm_code_end): Likewise.
	* config/loongarch/loongarch.opt: Likewise.
	* doc/invoke.texi: Likewise.

2024-04-22  Pan Li  <pan2.li@intel.com>

	* config/riscv/vector-crypto.md:

2024-04-22  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-11-30  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Fix constraint.
	* config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Rename vconstraint into group_overlap.
	(no,yes): Ditto.
	(none,W21,W42,W84,W43,W86,W87): Ditto.
	* config/riscv/vector.md: Ditto.

2024-04-22  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.md: Rostify the constraints.

2024-04-22  Haochen Jiang  <haochen.jiang@intel.com>

	* common/config/i386/i386-common.cc (processor_alias_table):
	Let Sierra Forest map to CPU_TYPE enum.

2024-04-22  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/s390/s390.cc (s390_option_override_internal): Check zarch
	flag before enabling -mvx.

2024-04-22  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-11-30  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Add widenning overlap.

2024-04-22  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-01  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Support highpart overlap for indexed load.

2024-04-22  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Add highest-number overlap support.

2024-04-22  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-11-30  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Add widening overlap of vf2/vf4.

2024-04-21  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-01  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Support highpart overlap for vx/vf.

2024-04-20  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Fix incorrect overlap in v0.

2024-04-20  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112431
	* config/riscv/vector.md: Support highest overlap for wv instructions.

2024-04-20  Pan Li  <pan2.li@intel.com>

	Revert:
	2023-12-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/112432
	* config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87): Add W0.
	(none,W21,W42,W84,W43,W86,W87,W0): Ditto.
	* config/riscv/vector.md: Ditto.

2024-04-19  Jakub Jelinek  <jakub@redhat.com>

	PR target/114783
	* config/i386/sse.md (*avx2_eq<mode>3): Change last operand's
	constraint from "jm" to "xjm".

2024-04-19  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114753
	* internal-fn.cc (expand_arith_overflow): Add one missing restore
	of flag_trapv before return.

2024-04-19  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/114769
	* tree-vect-patterns.cc:
	(vect_recog_absolute_difference): Have only one success condition.
	(vect_recog_abd_pattern): Handle further checks if
	vect_recog_absolute_difference fails.

2024-04-19  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/core-builtins.cc (get_index_for_enum_value): Create
	function.
	(pack_enum_value): Check for enumerator and error out.
	(process_enum_value): Correct string allocation.

2024-04-19  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/bpf-protos.h (bpf_add_core_reloc): Renamed function
	to bpf_output_move.
	* config/bpf/bpf.cc (bpf_legitimate_address_p): Allow
	UNSPEC_CORE_RELOC to match an address.
	(bpf_insn_cost): Make UNSPEC_CORE_RELOC immediate moves
	expensive to prioritize loads and stores.
	(TARGET_INSN_COST): Add hook.
	(bpf_output_move): Wrapper to call bpf_output_core_reloc.
	(bpf_print_operand): Add support to print immediate operands
	specified with the UNSPEC_CORE_RELOC.
	(bpf_print_operand_address): Likewise, but to support
	UNSPEC_CORE_RELOC in addresses.
	(bpf_init_builtins): Flag BPF_BUILTIN_CORE_RELOC as NOTHROW.
	* config/bpf/bpf.md: Wrap patterns for MOV, LD and ST
	instruction with bpf_output_move call.
	(mov_reloc_core<MM:mode>): Remove now spurious define_insn.
	* config/bpf/constraints.md: Added "c" and "C" constraints to
	match immediates represented with UNSPEC_CORE_RELOC.
	* config/bpf/core-builtins.cc (bpf_add_core_reloc): Remove
	(bpf_output_core_reloc): Add function to create the CO-RE
	relocations based on new matching rules.
	* config/bpf/core-builtins.h (bpf_output_core_reloc): Add
	prototype.
	* config/bpf/predicates.md (core_imm_operand) Add predicate.
	(mov_src_operand): Add match for core_imm_operand.

2024-04-19  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/114768
	* rtlanal.cc (set_noop_p): Don't return true for MEM <- MEM
	sets if src has side-effects or for stores into ZERO_EXTRACT
	if ZERO_EXTRACT operand has side-effects.

2024-04-19  Alexandre Oliva  <oliva@adacore.com>

	* config/t-vxworks (vxw-glimits.h): Don't mangle c23-required
	__STDC_VERSION_LIMITS_H__ define.

2024-04-18  Sandra Loosemore  <sloosemore@baylibre.com>

	* config.gcc: Add nios2*-*-* to the list of obsoleted targets.

2024-04-18  Alexandre Oliva  <oliva@adacore.com>

	* doc/sourcebuild.texi (strndup): Add effective target.

2024-04-18  Tamar Christina  <tamar.christina@arm.com>

	PR target/114741
	* config/aarch64/aarch64.md (<optab><mode>3): Remove ^ from alt 2.
	(copysign<GPF:mode>3): Use SIMD version of IOR directly.

2024-04-18  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114753
	* internal-fn.cc (expand_mul_overflow): Save flag_trapv and
	temporarily clear it for the duration of the function, then
	restore previous value.
	(expand_vector_ubsan_overflow): Likewise.
	(expand_arith_overflow): Likewise.

2024-04-17  Jakub Jelinek  <jakub@redhat.com>

	PR other/114738
	* opts.cc (get_option_url): On release branches append
	gcc-MAJOR.MINOR.0/ after DOCUMENTATION_ROOT_URL.
	* gcc-urlifier.cc (gcc_urlifier::make_doc_url): Likewise.

2024-04-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114749
	* tree-vect-loop.cc (vect_analyze_loop_2): Reset
	LOOP_VINFO_USING_PARTIAL_VECTORS_P when re-trying without SLP.

2024-04-17  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114752
	* config/avr/avr.cc (avr_print_operand) [CONST_DOUBLE_P]: Handle DFmode.

2024-04-17  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/114743
	* asan.cc (maybe_instrument_call): Don't instrument calls to
	.ABNORMAL_DISPATCHER.

2024-04-16  Andrew Pinski  <quic_apinski@quicinc.com>

	PR c/92880
	* doc/extend.texi (Using Vector Instructions): Add that
	the base_types could be a typedef of them.

2024-04-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114736
	* tree-vect-slp.cc (vect_optimize_slp_pass::is_cfg_latch_edge):
	Do not consider VEC_PERM_EXPRs as PHI use.

2024-04-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114733
	* tree-vect-loop.cc (vectorizable_nonlinear_induction): Reject
	neg induction vectorization of single element vectors.

2024-04-16  Jakub Jelinek  <jakub@redhat.com>

	* tree.cc (array_type_nelts): Ensure 2 spaces after . in comment
	instead of just one.
	(build_variant_type_copy): Likewise.
	(tree_check_failed): Likewise.
	(build_atomic_base): Likewise.
	* ipa-free-lang-data.cc (fld_incomplete_type_of): Use an indefinite
	article rather than a.

2024-04-16  Fei Gao  <gaofei@eswincomputing.com>

	* config/riscv/riscv.cc (riscv_expand_conditional_move):
	replace or with add when expanding zicond if possible.

2024-04-16  Alexandre Oliva  <oliva@adacore.com>

	PR middle-end/112938
	* ipa-strub.cc (pass_ipa_strub::execute): Drop volatility from
	indirected parm.
	(maybe_make_indirect): Restore volatility in dereferences.

2024-04-16  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.opt.urls: Regenerate.
	* config/mn10300/mn10300.opt.urls: Likewise.
	* config/msp430/msp430.opt.urls: Likewise.
	* config/nds32/nds32-elf.opt.urls: Likewise.
	* config/nds32/nds32-linux.opt.urls: Likewise.
	* config/nds32/nds32.opt.urls: Likewise.
	* config/pru/pru.opt.urls: Likewise.
	* config/riscv/riscv.opt.urls: Likewise.
	* config/rx/rx.opt.urls: Likewise.
	* config/sh/sh.opt.urls: Likewise.
	* config/sparc/sparc.opt.urls: Likewise.
	* doc/invoke.texi: Add indexes for some compilation options.

2024-04-15  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-mcus.def: Add: avr16du14, avr16du20, avr16du28,
	avr16du32, avr32du14, avr32du20, avr32du28,  avr32du32.
	* doc/avr-mmcu.texi: Rebuild.

2024-04-15  Robin Dapp  <rdapp@ventanamicro.com>

	PR target/114668
	* config/riscv/autovec.md: Add VLS.

2024-04-15  Richard Biener  <rguenther@suse.de>

	PR gcov-profile/114715
	* gimplify.cc (gimplify_switch_expr): Set the location of the
	GIMPLE switch.

2024-04-15  H.J. Lu  <hjl.tools@gmail.com>

	PR target/114696
	* config/i386/i386.md (isa): Add apx_ndd_64.
	(enabled): Likewise.
	(*add<dwi>3_doubleword): Change rjO to r,ro,jO with 8-bit
	signed integer constant and enable jO only for apx_ndd_64.
	(*add<dwi>3_doubleword_cc_overflow_1): Likewise.
	(*and<dwi>3_doubleword): Likewise.
	(*<code><dwi>3_doubleword): Likewise.

2024-04-15  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/114403
	* tree-vect-loop.cc (vect_transform_loop): Adjust upper bounds for when
	peeling for gaps and early break.

2024-04-15  Jakub Jelinek  <jakub@redhat.com>

	PR c++/114634
	* attribs.cc (diag_attr_exclusions): Set attrs[1] to NULL_TREE for
	decls with NULL TREE_TYPE.

2024-04-12  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-option-extensions.def: Add RCPC to
	RCPC3 dependencies.
	* config/aarch64/aarch64.h (AARCH64_ISA_RCPC8_4): Add test for
	RCPC3 bit

2024-04-12  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-arches.def: Add CSSC to V8_9A
	dependencies.

2024-04-12  Will Schmidt  <will_schmidt@linux.ibm.com>
	    Peter Bergner  <bergner@linux.ibm.com>

	PR target/101865
	* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
	TARGET_POWER8.
	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
	OPTION_MASK_POWER8.
	* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8.
	(ISA_2_7_MASKS_SERVER): Likewise.
	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
	comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
	* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
	* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
	(define_attr "enabled"): Handle it.
	(define_insn "prefetch"): Use TARGET_POWER8.
	* config/rs6000/rs6000.opt (mpower8-internal): New.

2024-04-12  Jason Merrill  <jason@redhat.com>
	    Patrick Palka  <ppalka@redhat.com>

	PR c++/113141
	* doc/invoke.texi: Document -Wcast-user-defined.

2024-04-12  Tatsuyuki Ishi  <ishitatsuyuki@gmail.com>

	* config/riscv/riscv.opt.urls: Regenerated.

2024-04-12  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/114666
	* match.pd (`!a?b:c`): Reject signed types for the condition.
	(`a?~t:t`): Likewise.

2024-04-12  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Require
	all tiles to have the same suffix.

2024-04-12  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv.cc (riscv_vector_float_type_p): Take int
	as the return value instead of unsigned.
	(riscv_vector_element_bitsize): Ditto.
	(riscv_vector_required_min_vlen): Ditto.
	(riscv_validate_vector_type): Take int type for local variable(s).

2024-04-12  Jakub Jelinek  <jakub@redhat.com>

	* tree-cfg.cc (gimple_verify_flow_info): Make the misplaced
	returns_twice diagnostics translatable.

2024-04-12  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/114687
	* gimple-iterator.cc (gsi_safe_insert_before): Only use
	edge_before_returns_twice_call if bb_has_abnormal_pred.
	(gsi_safe_insert_seq_before): Likewise.
	* gimple-lower-bitint.cc (bitint_large_huge::lower_call): Only
	push to m_returns_twice_calls if bb_has_abnormal_pred.

2024-04-12  Pan Li  <pan2.li@intel.com>

	PR target/114639
	* config/riscv/riscv.cc (riscv_function_value_regno_p): Add
	TARGET_VECTOR predicate for V_RETURN regno.

2024-04-11  David Faust  <david.faust@oracle.com>

	* btfout.cc (btf_asm_type_ref): Convert IDs to BTF internally and
	fix potentially looking up wrong type for asm debug comment info.
	Split into...
	(btf_asm_datasec_type_ref): ... This. New.
	(btf_asm_datasec_entry): Call it here, instead of btf_asm_type_ref.
	(btf_asm_type, btf_asm_array, btf_asm_varent, btf_asm_sou_member)
	(btf_asm_func_arg, btf_asm_func_type): Adapt btf_asm_type_ref call.

2024-04-11  David Faust  <david.faust@oracle.com>

	* btfout.cc (btf_asm_sou_member): Always emit non-representable
	bitfield members as having 'void' type.  Refactor slightly.

2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-option-extensions.def:
	Remove "memtag", "memtag2", "ssbs", "ssbs2", "ls64", "ls64_v"
	and "ls64_accdata" FMV features.

2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-option-extensions.def:
	Remove "flagm2", "sha1", "pmull", "dit", "dpb", "dpb2", "jscvt",
	"fcma", "rcpc2", "frintts", "dgh", "ebf16", "sve-bf16",
	"sve-ebf16", "sve-i8mm", "sve2-pmull128", "memtag3", "bti" and
	"wfxt" entries.

2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-option-extensions.def:
	Fix "rmd"->"rdm", and add FMV to "rdma".
	* config/aarch64/aarch64.cc (FEAT_RDMA): Define as FEAT_RDM.

2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.cc (compare_feature_masks):
	Use ARRAY_SIZE and >=0 for iteration bounds.
	(aarch64_mangle_decl_assembler_name): Use ARRAY_SIZE.

2024-04-11  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64-option-extensions.def: Reorder FMV entries.

2024-04-11  Gaius Mulley  <gaiusmod2@gmail.com>

	* doc/standards.texi (Language Standards Supported by GCC):
	Add Modula-2 language section.

2024-04-11  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/110027
	* asan.cc (asan_emit_stack_protection): Assert offsets[0] is
	zero if there is no stack protect guard, otherwise
	-ASAN_RED_ZONE_SIZE.  If alignb > ASAN_RED_ZONE_SIZE and there is
	stack pointer guard, take the ASAN_RED_ZONE_SIZE bytes allocated at
	the top of the stack into account when computing base_align_bias.
	Recompute use_after_return_class from asan_frame_size + base_align_bias
	and set to -1 if that would overflow to 11.

2024-04-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/109596
	* tree-ssa-loop-ch.cc (ch_base::copy_headers): Propagate
	debug stmts to nonexit->dest rather than exit->dest.

2024-04-11  Richard Biener  <rguenther@suse.de>

	PR middle-end/114681
	* tree-inline.cc (copy_bb): Key on the remapped stmt
	to identify gconds to have condition coverage data remapped.

2024-04-11  Pan Li  <pan2.li@intel.com>

	PR target/114639
	* config/riscv/riscv.cc (riscv_function_value_regno_p): New func
	impl for hook TARGET_FUNCTION_VALUE_REGNO_P.
	(riscv_get_raw_result_mode): New func imple for hook
	TARGET_GET_RAW_RESULT_MODE.
	(TARGET_FUNCTION_VALUE_REGNO_P): Impl the hook.
	(TARGET_GET_RAW_RESULT_MODE): Ditto.
	* config/riscv/riscv.h (V_RETURN): New macro for vector return.
	(GP_RETURN_FIRST): New macro for the first GPR in return.
	(GP_RETURN_LAST): New macro for the last GPR in return.
	(FP_RETURN_FIRST): Diito but for FPR.
	(FP_RETURN_LAST): Ditto.
	(FUNCTION_VALUE_REGNO_P): Remove as deprecated and replace by
	TARGET_FUNCTION_VALUE_REGNO_P.

2024-04-11  Indu Bhagat  <indu.bhagat@oracle.com>

	* btfout.cc (btf_asm_type): Do not skip emitting members of
	unknown type.

2024-04-11  Indu Bhagat  <indu.bhagat@oracle.com>

	PR debug/112878
	* dwarf2ctf.cc (gen_ctf_sou_type): Check for conditions before
	call to ctf_add_slice.  Use CTF_K_UNKNOWN type if fail.

2024-04-10  Marek Polacek  <polacek@redhat.com>

	PR target/114606
	* config/i386/i386-options.cc (ix86_option_override_internal): Use
	opts_set rather than checking == CF_NONE.

2024-04-10  David Malcolm  <dmalcolm@redhat.com>

	* doc/analyzer.texi: Various tweaks.

2024-04-10  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114672
	* tree-ssa-math-opts.cc (convert_plusminus_to_widen): Only
	allow mode-precision results.

2024-04-10  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/aarch64/aarch64.cc (TARGET_C_BITINT_TYPE_INFO): Declare MACRO.
	(aarch64_bitint_type_info): New function.
	(aarch64_return_in_memory_1): Return large _BitInt's in memory.
	(aarch64_function_arg_alignment): Adapt to correctly return the ABI
	mandated alignment of _BitInt(N) where N > 128 as the alignment of
	TImode.
	(aarch64_composite_type_p): Return true for _BitInt(N), where N > 128.

2024-04-10  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/aarch64/aarch64.cc (bitint_or_aggr_of_bitint_p): New function.
	(aarch64_layout_arg): Don't emit diagnostics for types involving
	_BitInt(N).

2024-04-10  Jakub Jelinek  <jakub@redhat.com>

	PR c++/114462
	* tree-core.h (enum annot_expr_kind): Add
	annot_expr_maybe_infinite_kind enumerator.
	* gimplify.cc (gimple_boolify): Handle annot_expr_maybe_infinite_kind.
	* tree-cfg.cc (replace_loop_annotate_in_block): Likewise.
	(replace_loop_annotate): Likewise.  Move loop->finite_p initialization
	before the replace_loop_annotate_in_block calls.
	* tree-pretty-print.cc (dump_generic_node): Handle
	annot_expr_maybe_infinite_kind.

2024-04-10  Richard Biener  <rguenther@suse.de>

	Revert:
	2024-03-27  Segher Boessenkool  <segher@kernel.crashing.org>

	PR rtl-optimization/101523
	* combine.cc (try_combine): Don't do a 2-insn combination if
	it does not in fact change I2.

2024-04-10  Peter Bergner  <bergner@linux.ibm.com>

	PR target/101865
	* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
	OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete redundant
	OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
	(rs6000_opt_masks): Neuter the "direct-move" option.
	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
	OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
	comment.
	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
	OPTION_MASK_DIRECT_MOVE.
	(OTHER_VSX_VECTOR_MASKS): Likewise.
	(POWERPC_MASKS): Likewise.
	* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

2024-04-10  Hongyu Wang  <hongyu.wang@intel.com>

	* config/i386/sse.md (sha1msg1): Use "ja" instead of "Bm" for
	memory constraint.
	(sha1msg2): Likewise.
	(sha1nexte): Likewise.
	(sha1rnds4): Likewise.
	(sha256msg1): Likewise.
	(sha256msg2): Likewise.
	(sha256rnds2): Likewise.
	(aes<aesklvariant>u8): Use "jm" instead of "m" for memory
	constraint.
	(*aes<aeswideklvariant>u8): Likewise.
	(*encodekey128u32): Use "jr" instead of "r" for register
	constraints.
	(*encodekey256u32): Likewise.

2024-04-09  Juergen Christ  <jchrist@linux.ibm.com>

	* config/s390/s390.cc (expand_perm_as_replicate): Implement.
	(vectorize_vec_perm_const_1): Call new function.
	* config/s390/vx-builtins.md (vec_splat<mode>): Change to...
	(@vec_splat<mode>): ...this.

2024-04-09  David Faust  <david.faust@oracle.com>

	PR debug/114608
	* btfout.cc (btf_asm_datasec_entry): Only emit a symbol reference when
	generating BTF for BPF CO-RE target.

2024-04-09  Richard Ball  <richard.ball@arm.com>

	* config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64):
	Add functions_nulls parameter to pragma_handlers.
	* config/aarch64/aarch64-protos.h: Likewise.
	* config/aarch64/aarch64-sve-builtins.h
	(enum handle_pragma_index): Add enum to count
	number of pragmas to be handled.
	* config/aarch64/aarch64-sve-builtins.cc
	(GTY): Add global variable for initial indexes
	and change overload_names to an array.
	(function_builder::function_builder):
	Add pragma handler information.
	(function_builder::add_function):
	Add code for overwriting previous
	registered_functions entries.
	(add_unique_function):
	Use an array to register overload_names
	for both pragma handler modes.
	(add_overloaded_function): Likewise.
	(init_builtins):
	Add functions_nulls parameter to pragma_handlers.
	(handle_arm_sve_h):
	Initialize pragma handler information.
	(handle_arm_neon_sve_bridge_h): Likewise.
	(handle_arm_sme_h): Likewise.

2024-04-09  Richard Biener  <rguenther@suse.de>

	PR lto/114655
	* lto-wrapper.cc (merge_flto_options): Add force argument.
	(merge_and_complain): Do not force here.
	(run_gcc): But here to make the link-time -flto option override
	any compile-time one.

2024-04-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>

	* config/rs6000/rtems.h (OS_MISSING_POWERPC64): Define.

2024-04-09  Jørgen Kvalsvik  <j@lambda.is>

	PR gcov-profile/114601
	* tree-profile.cc (condition_uid): Guard fn->cond_uids access.

2024-04-09  Jakub Jelinek  <jakub@redhat.com>

	PR target/114576
	* config/i386/i386.md (isa): Remove aes, add vaes_avx512vl.
	(enabled): Remove aes isa check, add vaes_avx512vl.
	* config/i386/sse.md (aesenc, aesenclast, aesdec, aesdeclast): Use
	jm instead of m for second alternative and emit {evex} prefix
	for it if !TARGET_AES.  Use noavx,avx,vaes_avx512vl isa attribute.
	(vaesdec_<mode>, vaesdeclast_<mode>, vaesenc_<mode>,
	vaesenclast_<mode>): Add second alternative with x instead of v
	and jm instead of m.

2024-04-09  Gaius Mulley  <gaiusmod2@gmail.com>

	* doc/gm2.texi (Compiler options): Remove -fdebug-trace-quad.
	Remove -fdebug-trace-api.
	Add -fm2-debug-trace=.

2024-04-09  Yang Yujie  <yangyujie@loongson.cn>

	PR target/113233
	* config/loongarch/loongarch.cc (loongarch_reg_init):
	Reinitialize the loongarch_regno_mode_ok cache.
	(loongarch_option_override): Same.
	(loongarch_save_restore_target_globals): Restore target globals.
	(loongarch_set_current_function): Restore the target contexts
	for functions.
	(TARGET_SET_CURRENT_FUNCTION): Define.
	* config/loongarch/loongarch.h (SWITCHABLE_TARGET): Enable
	switchable target context.
	* config/loongarch/loongarch-builtins.cc (loongarch_init_builtins):
	Initialize all builtin functions at startup.
	(loongarch_expand_builtin): Turn assertion of builtin availability
	into a test.

2024-04-09  Jørgen Kvalsvik  <j@lambda.is>

	PR middle-end/114627
	* tree-profile.cc (instrument_decisions): Generate constant
	at the start of loop.

2024-04-09  Jørgen Kvalsvik  <j@lambda.is>

	PR middle-end/114599
	* tree-inline.cc (copy_bb): Copy cond_uids into callee.
	(prepend_lexical_block): Remove outdated comment.
	(add_local_variables): Remove bad cond_uids copy.

2024-04-09  Jakub Jelinek  <jakub@redhat.com>

	* expr.cc (convert_mode_scalar): Fix duplicated words in comment;
	into into -> it into.
	* function.h (function::cond_uids): Fix duplicated words in comment;
	same same -> same.
	* config/riscv/riscv-vector-costs.cc
	(costs::adjust_vect_cost_per_loop): Fix duplicated words in comment;
	model model -> model.
	* config/riscv/riscv-vector-builtins-shapes.cc (build_base): Fix
	duplicated words in comment; for for -> for.
	* config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Fix
	duplicated words in comment; more more -> more.
	* config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Fix
	duplicated words in comment; be be -> be.
	* tree-profile.cc (masking_vectors): Fix duplicated words in comment;
	has has -> has, the the -> the.
	* value-range.cc (irange::set_range_from_bitmask): Fix duplicated
	words in comment; the the -> the.
	* gcov.cc (add_condition_counts): Fix duplicated words in comment;
	to to -> to.
	* vr-values.cc (get_scev_info): Fix duplicated words in comment;
	the the -> to the.
	* tree-vrp.cc (fully_replaceable): Fix duplicated words in comment;
	by by -> by.
	* mode-switching.cc (single_succ_confluence_n): Fix duplicated words
	in comment; the the -> the.
	* tree-ssa-phiopt.cc (value_replacement): Fix duplicated words in
	comment; can can -> we can.
	* gimple-range-phi.cc (phi_analyzer::process_phi): Fix duplicated words
	in comment; it it -> it is.
	* tree-ssa-sccvn.cc (visit_phi): Fix duplicated words in comment;
	to to -> to.
	* rtl-ssa/accesses.h (use_info::next_debug_insn_use): Fix duplicated
	words in comment; if if -> if.
	* doc/options.texi (InverseMask): Fix duplicated words; and and -> and.
	Change take to takes.
	* doc/invoke.texi (fanalyzer-undo-inlining): Fix duplicated words;
	be be -> be.
	(-minline-memops-threshold): Likewise.

2024-04-09  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114628
	* gimple-lower-bitint.cc (gimple_lower_bitint): Keep debug stmts
	before returns_twice calls as is, don't push them into arg_stmts
	vector/move to edges.

2024-04-09  Sergey Bugaev  <bugaevc@gmail.com>

	* config.gcc: Recognize aarch64*-*-gnu* targets.
	* config/aarch64/aarch64-gnu.h: New file.

2024-04-09  Sergey Bugaev  <bugaevc@gmail.com>

	* config/i386/gnu.h: Move GNU/Hurd STARTFILE_SPEC from here...
	* config/gnu.h: ...to here.

2024-04-09  Richard Biener  <rguenther@suse.de>

	PR middle-end/114604
	* gimple-range.cc (enable_ranger): Initialize the global
	bitmap obstack.
	(disable_ranger): Release it.

2024-04-09  Sebastian Huber  <sebastian.huber@embedded-brains.de>

	* config.gcc (aarch64-*-rtems*): Add target makefile fragment
	t-aarch64-rtems.
	* config/aarch64/t-aarch64-rtems: New file.

2024-04-09  H.J. Lu  <hjl.tools@gmail.com>

	PR target/114587
	* config/i386/i386-c.cc (ix86_target_macros_internal): Define
	__APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32.

2024-04-09  Kewen Lin  <linkw@linux.ibm.com>
	    Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/88309
	* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Fix
	wrong align passed to function build_aligned_type.
	* tree-ssa-loop-prefetch.cc (is_miss_rate_acceptable): Add an
	assertion to ensure align_unit should be positive.
	* tree.cc (build_qualified_type): Update function comments.

2024-04-08  Uros Bizjak  <ubizjak@gmail.com>

	PR rtl-optimization/112560
	* combine.cc (try_combine): Replace cc_use_loc with the entire
	new RTX only in case cc_use_loc satisfies COMPARISON_P predicate.
	Otherwise scan the entire cc_use_loc RTX for CC reg to be updated
	with a new mode.
	* config/i386/i386.md (@pushf<mode>2): Allow all CC modes for
	operand 1.

2024-04-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor):
	New.
	* config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it.
	* doc/invoke.texi (Optimize Options): Document it.

2024-04-08  Thomas Schwinge  <tschwinge@baylibre.com>

	* doc/sourcebuild.texi (Effective-Target Keywords): Document
	'asm_goto_with_outputs'.  Add comment to 'lra'.

2024-04-08  Martin Jambor  <mjambor@suse.cz>

	PR ipa/113359
	* ipa-icf-gimple.h (func_checker): New members
	safe_for_total_scalarization_p, m_total_scalarization_limit_known_p
	and m_total_scalarization_limit.
	(func_checker::func_checker): Initialize new member variables.
	* ipa-icf-gimple.cc: Include tree-sra.h.
	(func_checker::func_checker): Initialize new member variables.
	(func_checker::safe_for_total_scalarization_p): New function.
	(func_checker::compare_operand): Use the new function.
	* tree-sra.h (sra_get_max_scalarization_size): Declare.
	(sra_total_scalarization_would_copy_same_data_p): Likewise.
	* tree-sra.cc (prepare_iteration_over_array_elts): New function.
	(class sra_padding_collecting): New.
	(sra_padding_collecting::record_padding): Likewise.
	(scalarizable_type_p): Rename to totally_scalarizable_type_p.  Add
	ability to record padding when requested.
	(totally_scalarize_subtree): Split out gathering information necessary
	to iterate over array elements to prepare_iteration_over_array_elts.
	Fix errornous early exit.
	(analyze_all_variable_accesses): Adjust the call to
	totally_scalarizable_type_p.  Move determining of total scalariation
	size limit...
	(sra_get_max_scalarization_size): ...here.
	(check_ts_and_push_padding_to_vec): New function.
	(sra_total_scalarization_would_copy_same_data_p): Likewise.

2024-04-08  Martin Jambor  <mjambor@suse.cz>

	PR ipa/113907
	* ipa-prop.h (class ipa_vr): Declare new overload of a member function
	equal_p.
	(ipa_jump_functions_equivalent_p): Declare.
	* ipa-prop.cc (ipa_vr::equal_p): New function.
	(ipa_agg_pass_through_jf_equivalent_p): Likewise.
	(ipa_agg_jump_functions_equivalent_p): Likewise.
	(ipa_jump_functions_equivalent_p): Likewise.
	* ipa-cp.h (values_equal_for_ipcp_p): Declare.
	* ipa-cp.cc (values_equal_for_ipcp_p): Make function public.
	* ipa-icf-gimple.cc: Include alloc-pool.h, symbol-summary.h, sreal.h,
	ipa-cp.h and ipa-prop.h.
	(func_checker::compare_gimple_call): Comapre jump functions.

2024-04-08  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/114607
	* config/aarch64/aarch64-sve-builtins-base.cc
	(svusdot_impl::expand): Fix botched attempt to swap the operands
	for svsudot.

2024-04-08  Tatsuyuki Ishi  <ishitatsuyuki@gmail.com>

	* config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
	* config.gcc: Add --with-tls configuration option to change the
	default TLS flavor.
	* config/riscv/riscv.h: Add TARGET_TLSDESC determined from
	-mtls-dialect and with_tls defaults.
	* config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
	two TLS flavors.
	* config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
	* config/riscv/riscv.md: Add instruction sequence for TLSDESC.
	* config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
	sequence length data for TLSDESC.
	(riscv_legitimize_tls_address): Add lowering of TLSDESC.
	* doc/install.texi: Document --with-tls for RISC-V.
	* doc/invoke.texi: Document -mtls-dialect for RISC-V.

2024-04-08  Jakub Jelinek  <jakub@redhat.com>

	PR target/114605
	* config/s390/s390.cc (s390_const_int_pool_entry_p): Punt
	if mem doesn't have MODE_INT mode, or pool constant doesn't
	have MODE_INT mode, or if pool constant mode is smaller than
	mem mode.  If mem mode is different from pool constant mode,
	try to simplify subreg.  If that doesn't work, punt, if it
	does, use the simplified constant instead of the constant pool
	constant.
	* config/s390/s390.md (movdi from const pool peephole): If
	either low or high 32-bit part is zero, just emit move insn
	instead of move + ior.

2024-04-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114624
	* tree-scalar-evolution.cc (final_value_replacement_loop):
	Get at the PHI arg location before releasing the PHI node.

2024-04-08  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-vector-builtins-shapes.cc (build_one): Pass
	required_ext arg when invoke add function.
	(build_th_loadstore): Ditto.
	(struct vcreate_def): Ditto.
	(struct read_vl_def): Ditto.
	(struct vlenb_def): Ditto.
	* config/riscv/riscv-vector-builtins.cc (function_builder::add_function):
	Introduce new arg required_ext to fill in the register func.
	(function_builder::add_unique_function): Ditto.
	(function_builder::add_overloaded_function): Ditto.
	(expand_builtin): Leverage required_extensions_specified to
	check if the required extension is provided.
	* config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): New
	func impl to convert the required_ext enum to the extension name.
	(required_extensions_specified): New func impl to predicate if
	the required extension is well feeded.

2024-04-08  Iain Sandoe  <iain@sandoe.co.uk>

	* config/darwin.h (LINK_COMMAND_SPEC_A): Update coverage
	specs.

2024-04-08  demin.han  <demin.han@starfivetech.com>

	* config/riscv/riscv-vector-costs.cc: Use length()

2024-04-08  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): New
	struct to hold all intrinisc related flags.
	(riscv_pragma_intrinsic_flags_pollute): New func to pollute
	the intrinsic flags and backup original flags.
	(riscv_pragma_intrinsic_flags_restore): New func to restore
	the flags from the backup intrinsic flags.
	(riscv_pragma_intrinsic): Pollute the flags and register all
	possible builtin types and functions, then restore and reinit.
	* config/riscv/riscv-protos.h (reinit_builtins): New func
	decl to reinit after flags pollution.
	(riscv_option_override): New extern func decl.
	* config/riscv/riscv-vector-builtins.cc (register_builtin_types_on_null):
	New func to register builtin types if null.
	(DEF_RVV_TYPE): Ditto.
	(DEF_RVV_TUPLE_TYPE): Ditto.
	(reinit_builtins): New func impl to reinit after flags pollution.
	(expand_builtin): Return
	target rtx after error_at.
	* config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate
	func to tell one tree type is integer or not.
	(riscv_vector_float_type_p): New predicate func to tell one tree
	type is float or not.
	(riscv_vector_element_bitsize): New func to get the element bitsize
	of a vector tree type.
	(riscv_vector_required_min_vlen): New func to get the required min vlen
	of a vector tree type.
	(riscv_validate_vector_type): New func to validate the tree type
	is valid on flags.
	(riscv_return_value_is_vector_type_p): Leverage the func
	riscv_validate_vector_type to do the tree type validation.
	(riscv_arguments_is_vector_type_p): Ditto.
	(riscv_override_options_internal): Ditto.

2024-04-08  Lulu Cheng  <chenglulu@loongson.cn>

	PR target/112919
	* config/loongarch/loongarch-def.cc (la664_align): Newly defined
	function that sets alignment rules under the LA664 microarchitecture.
	* config/loongarch/loongarch-opts.cc
	(loongarch_target_option_override): If not optimizing for size, set
	the default alignment to what the target wants.
	* config/loongarch/loongarch-tune.h (struct loongarch_align): Add
	new member variables jump and loop.

2024-04-06  H.J. Lu  <hjl.tools@gmail.com>

	PR target/114590
	* config/i386/i386.md (x86_64_shld): Use explicit shift count in
	AT&T syntax.
	(x86_64_shld_ndd): Likewise.
	(x86_shld): Likewise.
	(x86_shld_ndd): Likewise.
	(x86_64_shrd): Likewise.
	(x86_64_shrd_ndd): Likewise.
	(x86_shrd): Likewise.
	(x86_shrd_ndd): Likewise.

2024-04-06  Jørgen Kvalsvik  <j@lambda.is>

	PR middle-end/114599
	* tree-inline.cc (add_local_variables): Copy cond_uids mappings.

2024-04-05  David Malcolm  <dmalcolm@redhat.com>

	PR analyzer/114588
	* diagnostic-color.cc (color_dict): Add "valid" and "invalid" as
	color capability names.
	* doc/invoke.texi: Document them in description of GCC_COLORS.
	* text-art/style.cc: Include "diagnostic-color.h".
	(text_art::get_style_from_color_cap_name): New.
	* text-art/types.h (get_style_from_color_cap_name): New decl.

2024-04-05  Alex Coplan  <alex.coplan@arm.com>

	* config/aarch64/aarch64-ldp-fusion.cc (struct alias_walker):
	Fix double space after const qualifier on valid ().

2024-04-05  Martin Jambor  <mjambor@suse.cz>

	PR ipa/113964
	* ipa-param-manipulation.cc (ipa_param_adjustments::modify_call):
	Force values obtined through pass-through maps to the expected
	split type.

2024-04-05  Mark Wielaard  <mark@klomp.org>

	* common.opt.urls: Regenerate.

2024-04-05  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/114603
	* config/aarch64/aarch64-sve.md (@aarch64_pred_cnot<mode>): Replace
	with...
	(@aarch64_ptrue_cnot<mode>): ...this, requiring operand 1 to be
	a ptrue.
	(*cnot<mode>): Require operand 1 to be a ptrue.
	* config/aarch64/aarch64-sve-builtins-base.cc (svcnot_impl::expand):
	Use aarch64_ptrue_cnot<mode> for _x operations that are predicated
	with a ptrue.  Represent other _x operations as fully-defined _m
	operations.

2024-04-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114566
	* tree-vect-loop.cc (update_epilogue_loop_vinfo): Don't clear
	base_misaligned.

2024-04-05  Richard Biener  <rguenther@suse.de>

	PR middle-end/114599
	PR gcov-profile/114115
	* symtab.cc (ifunc_ref_map): Do not use auto_bitmap.
	(is_caller_ifunc_resolver): Optimize bitmap_bit_p/bitmap_set_bit
	pair.
	(symtab_node::check_ifunc_callee_symtab_nodes): Properly
	allocate ifunc_ref_map here.

2024-04-04  Martin Jambor  <mjambor@suse.cz>

	PR ipa/111571
	* ipa-param-manipulation.cc
	(ipa_param_body_adjustments::common_initialization): Avoid creating
	duplicate replacement entries.

2024-04-04  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/114415
	* sched-deps.cc (add_insn_mem_dependence): Add memory check for mem argument.
	(sched_analyze_1): Treat stack pointer modification as memory read.
	(sched_analyze_2, sched_analyze_insn): Add memory guard for processing pending_read_mems.
	* sched-int.h (deps_desc): Add comment to pending_read_mems.

2024-04-04  Tobias Burnus  <tburnus@baylibre.com>

	* config/nvptx/mkoffload.cc (main): Call
	gcc_init_libintl and diagnostic_color_init.

2024-04-04  H.J. Lu  <hjl.tools@gmail.com>

	PR target/114587
	* config/i386/i386-c.cc (ix86_target_macros_internal): Define
	__APX_F__ when APX is enabled.

2024-04-04  Jørgen Kvalsvik  <j@lambda.is>

	* builtins.cc (expand_builtin_fork_or_exec): Check
	condition_coverage_flag.
	* collect2.cc (main): Add -fno-condition-coverage to OBSTACK.
	* common.opt: Add new options -fcondition-coverage and
	-Wcoverage-too-many-conditions.
	* doc/gcov.texi: Add --conditions documentation.
	* doc/invoke.texi: Add -fcondition-coverage documentation.
	* function.cc (free_after_compilation): Free cond_uids.
	* function.h (struct function): Add cond_uids.
	* gcc.cc: Link gcov on -fcondition-coverage.
	* gcov-counter.def (GCOV_COUNTER_CONDS): New.
	* gcov-dump.cc (tag_conditions): New.
	* gcov-io.h (GCOV_TAG_CONDS): New.
	(GCOV_TAG_CONDS_LENGTH): New.
	(GCOV_TAG_CONDS_NUM): New.
	* gcov.cc (class condition_info): New.
	(condition_info::condition_info): New.
	(condition_info::popcount): New.
	(struct coverage_info): New.
	(add_condition_counts): New.
	(output_conditions): New.
	(print_usage): Add -g, --conditions.
	(process_args): Likewise.
	(output_intermediate_json_line): Output conditions.
	(read_graph_file): Read condition counters.
	(read_count_file): Likewise.
	(file_summary): Print conditions.
	(accumulate_line_info): Accumulate conditions.
	(output_line_details): Print conditions.
	* gimplify.cc (next_cond_uid): New.
	(reset_cond_uid): New.
	(shortcut_cond_r): Set condition discriminator.
	(tag_shortcut_cond): New.
	(gimple_associate_condition_with_expr): New.
	(shortcut_cond_expr): Set condition discriminator.
	(gimplify_cond_expr): Likewise.
	(gimplify_function_tree): Call reset_cond_uid.
	* ipa-inline.cc (can_early_inline_edge_p): Check
	condition_coverage_flag.
	* ipa-split.cc (pass_split_functions::gate): Likewise.
	* passes.cc (finish_optimization_passes): Likewise.
	* profile.cc (struct condcov): New declaration.
	(cov_length): Likewise.
	(cov_blocks): Likewise.
	(cov_masks): Likewise.
	(cov_maps): Likewise.
	(cov_free): Likewise.
	(instrument_decisions): New.
	(read_thunk_profile): Control output to file.
	(branch_prob): Call find_conditions, instrument_decisions.
	(init_branch_prob): Add total_num_conds.
	(end_branch_prob): Likewise.
	* tree-core.h (struct tree_exp): Add condition_uid.
	* tree-profile.cc (struct conds_ctx): New.
	(CONDITIONS_MAX_TERMS): New.
	(EDGE_CONDITION): New.
	(topological_cmp): New.
	(index_of): New.
	(single_p): New.
	(single_edge): New.
	(contract_edge_up): New.
	(struct outcomes): New.
	(conditional_succs): New.
	(condition_index): New.
	(condition_uid): New.
	(masking_vectors): New.
	(emit_assign): New.
	(emit_bitwise_op): New.
	(make_top_index_visit): New.
	(make_top_index): New.
	(paths_between): New.
	(struct condcov): New.
	(cov_length): New.
	(cov_blocks): New.
	(cov_masks): New.
	(cov_maps): New.
	(cov_free): New.
	(find_conditions): New.
	(struct counters): New.
	(find_counters): New.
	(resolve_counter): New.
	(resolve_counters): New.
	(instrument_decisions): New.
	(tree_profiling): Check condition_coverage_flag.
	(pass_ipa_tree_profile::gate): Likewise.
	* tree.h (SET_EXPR_UID): New.
	(EXPR_COND_UID): New.

2024-04-04  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/114577
	* config/aarch64/aarch64-sve-builtins.h (aarch64_sve::lookup_fndecl):
	Declare.
	* config/aarch64/aarch64-sve-builtins.cc (aarch64_sve::lookup_fndecl):
	New function.
	* config/aarch64/aarch64-sve-builtins-base.cc (is_undef): Likewise.
	(svset_neonq_impl::expand): Optimise expansions whose first argument
	is undefined.

2024-04-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114485
	* tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
	vect_step_op_neg isn't OK for partial vectors but only
	for unknown niter.

2024-04-04  Jakub Jelinek  <jakub@redhat.com>

	PR c++/114537
	* fold-const.cc (native_encode_initializer): Look through
	NON_LVALUE_EXPR if val is INTEGER_CST.

2024-04-04  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114555
	* gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
	m_bitfld_load and save_cast_conditional add any needed PHIs
	and adjust t4 accordingly.

2024-04-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114551
	* tree-ssa-loop-split.cc (split_loop): If the guard is
	only conditionally evaluated rewrite computations with
	possibly undefined overflow to unsigned arithmetic.

2024-04-04  Eugene Rozenfeld  <erozen@microsoft.com>

	PR gcov-profile/113765
	* auto-profile.cc (afdo_annotate_cfg): Don't set full_profile to true

2024-04-03  Mark Wielaard  <mark@klomp.org>

	* config/i386/i386.opt.urls: Regenerate.

2024-04-03  H.J. Lu  <hjl.tools@gmail.com>

	PR tree-optimization/114115
	* cgraph.h (symtab_node): Add check_ifunc_callee_symtab_nodes.
	(cgraph_node): Add called_by_ifunc_resolver.
	* cgraphunit.cc (symbol_table::compile): Call
	symtab_node::check_ifunc_callee_symtab_nodes.
	* symtab.cc (check_ifunc_resolver): New.
	(ifunc_ref_map): Likewise.
	(is_caller_ifunc_resolver): Likewise.
	(symtab_node::check_ifunc_callee_symtab_nodes): Likewise.
	* tree-profile.cc (gimple_gen_ic_func_profiler): Disable indirect
	call profiling for IFUNC resolvers and their callees.

2024-04-03  Tobias Burnus  <tburnus@baylibre.com>

	* lto-wrapper.cc (compile_offload_image): Prefix 'offload_args'
	suffix by the target name.

2024-04-03  Tobias Burnus  <tburnus@baylibre.com>

	* doc/install.texi (amdgcn-*-amdhsa): Update Newlib recommendation
	and update wording for LLVM 18 release.

2024-04-03  Tobias Burnus  <tburnus@baylibre.com>

	PR other/111966
	* config/gcn/mkoffload.cc (get_arch): New; moved -march= flag
	handling from ...
	(main): ... here; call it to handle --with-arch config option
	and -march= commandline.

2024-04-03  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114552
	* expr.cc (emit_push_insn): Only use store_constructor for
	immediate_const_ctor_p if int_expr_size matches size.

2024-04-03  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114557
	PR tree-optimization/114480
	* tree-phinodes.cc (release_phi_node): Return PHIs from
	allocation buckets not covered by free_phinodes to GC.
	(remove_phi_node): Release the PHI LHS before freeing the
	PHI node.
	* tree-vect-loop.cc (vectorizable_live_operation): Get PHI lhs
	before releasing it.

2024-04-03  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md: Remove unused code.
	* config/loongarch/loongarch-protos.h
	(loongarch_split_lsx_copy_d): Remove.
	(loongarch_split_lsx_insert_d): Ditto.
	(loongarch_split_lsx_fill_d): Ditto.
	* config/loongarch/loongarch.cc
	(loongarch_split_lsx_copy_d): Ditto.
	(loongarch_split_lsx_insert_d): Ditto.
	(loongarch_split_lsx_fill_d): Ditto.
	* config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter.
	(lsx_vpickve2gr_<lsxfmt_f>): Ditto.
	(abs<mode>2): Remove expander.
	(vabs<mode>2): Rename 2 abs<mode>2.

2024-04-02  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/aarch64/aarch64-option-extensions.def: Fix comment.

2024-04-02  Tom Tromey  <tromey@adacore.com>

	* dwarf2out.cc (print_dw_val) <dw_val_class_loc>: Don't
	print newline when not recursing.

2024-04-02  Iain Sandoe  <iain@sandoe.co.uk>

	* config/darwin.cc (darwin_override_options): Update the
	clang major version value in the dsymutil check.

2024-04-02  Iain Sandoe  <iain@sandoe.co.uk>

	* config/darwin.cc (darwin_override_options): Reduce the debug
	level to 2 if dsymutil cannot handle .macinfo sections.

2024-04-02  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/t-loongarch: Add loongarch-def-arrays.h
	to OPTION_H_EXTRA.

2024-04-02  mengqinggang  <mengqinggang@loongson.cn>
	    Lulu Cheng  <chenglulu@loongson.cn>
	    Xi Ruoyao  <xry111@xry111.site>

	* config.gcc: Add --with-tls option to change TLS flavor.
	* config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
	configure TLS flavor.
	* config/loongarch/loongarch-def.h (struct loongarch_target): Add
	tls_dialect.
	* config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
	flavor.
	* config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
	tls_dialect.
	(loongarch_config_target): Ditto.
	(loongarch_update_gcc_opt_status): Ditto.
	* config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto.
	(TARGET_TLS_DESC): New define.
	* config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS
	DESC instructions sequence length.
	(loongarch_legitimize_tls_address): New TLS DESC instruction sequence.
	(loongarch_option_override_internal): Add la_opt_tls_dialect.
	(loongarch_option_restore): Add la_target.tls_dialect.
	* config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal
	code model for TLS DESC.
	(got_load_tls_desc_off64): Extreme cmode model for TLS DESC.
	* config/loongarch/loongarch.opt: Regenerate.
	* config/loongarch/loongarch.opt.urls: Ditto.
	* doc/invoke.texi: Add a description of the compilation option
	'-mtls-dialect={trad,desc}'.

2024-04-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.opt.urls: Regenerate.

2024-04-01  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
	aliases to -mrecip={all,none}, respectively.
	* config/loongarch/loongarch.opt: Regenerate.
	* config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
	(ABI_FPU64_P): ...this.
	(ABI_FPU_32): Rename to...
	(ABI_FPU32_P): ...this.
	(ABI_FPU_NONE): Rename to...
	(ABI_NOFPU_P): ...this.
	(ABI_LP64_P): Define.
	* config/loongarch/loongarch.cc (loongarch_init_print_operand_punct):
	Merged into loongarch_global_init.
	(loongarch_cpu_option_override): Renamed to
	loongarch_target_option_override.
	(loongarch_option_override_internal): Move the work after
	loongarch_config_target into loongarch_target_option_override.
	(loongarch_global_init): Define.
	(INIT_TARGET_FLAG): Move to loongarch-opts.cc.
	(loongarch_option_override): Call loongarch_global_init
	separately.
	* config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme):
	Split the parsing of -mrecip=<string> from
	loongarch_option_override_internal.
	(loongarch_generate_mrecip_scheme): Define. Split from
	loongarch_option_override_internal.
	(loongarch_target_option_override): Define. Renamed from
	loongarch_cpu_option_override.
	(loongarch_init_misc_options): Define. Split from
	loongarch_option_override_internal.
	(INIT_TARGET_FLAG): Move from loongarch.cc.
	* config/loongarch/loongarch-opts.h (loongarch_target_option_override):
	New prototype.
	(loongarch_parse_mrecip_scheme): New prototype.
	(loongarch_init_misc_options): New prototype.
	(TARGET_ABI_LP64): Simplify with ABI_LP64_P.
	* config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
	Do not reference specific CPU architecture (LA664).
	(TARGET_RECIP_SQRT): Same.
	(TARGET_RECIP_RSQRT): Same.
	(TARGET_RECIP_VEC_DIV): Same.
	(TARGET_RECIP_VEC_SQRT): Same.
	(TARGET_RECIP_VEC_RSQRT): Same.

2024-04-01  Lulu Cheng  <chenglulu@loongson.cn>

	* doc/invoke.texi: Add descriptions for the compilation
	options.

2024-03-31  Jeff Law  <jlaw@ventanamicro.com>

	* config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
	and sfb_alu.

2024-03-31  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
	the term built-in over builtin.

2024-03-31  Pan Li  <pan2.li@intel.com>

	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
	Remove unused var decl.

2024-03-30  Xi Ruoyao  <xry111@xry111.site>

	PR target/114175
	* config/mips/mips.cc (mips_setup_incoming_varargs): Only skip
	mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
	functions if arg.type is NULL.

2024-03-29  Andrew Pinski  <quic_apinski@quicinc.com>

	* lto-compress.cc (lto_end_uncompression): Use
	fatal_error instead of internal_error when ZSTD
	is not enabled.

2024-03-28  Jeff Law  <jlaw@ventanamicro.com>

	* config/h8300/extensions.md (zero_extendqihi*): Add output
	template for reg->reg case where the regs don't match.

2024-03-28  Gaius Mulley  <(no_default)>

	PR modula2/114517
	* doc/gm2.texi: Mention gm2 treats a # in the first column
	as a preprocessor directive unless -fno-cpp is supplied.

2024-03-28  Jakub Jelinek  <jakub@redhat.com>

	* predict.cc (estimate_bb_frequencies): Fix comment typo,
	scalling -> scaling.

2024-03-28  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/112303
	* profile-count.h (profile_count::operator+): Perform
	addition in uint64_t variable and set m_val to MIN of that
	val and max_count.
	(profile_count::operator+=): Likewise.
	(profile_count::operator-=): Formatting fix.
	(profile_count::apply_probability): Use safe_scale_64bit
	even in the int overload.

2024-03-28  Jan Hubicka  <jh@suse.cz>

	PR middle-end/113907
	* ipa-icf.cc (sem_function::init): Hash PHI operands
	(sem_function::compare_phi_node): Add argument about preserving order

2024-03-28  Richard Biener  <rguenther@suse.de>

	PR middle-end/114480
	* cfganal.cc (compute_idf): Use simpler bitmap iteration,
	touch work_set only when phi_insertion_points changed.

2024-03-28  Palmer Dabbelt  <palmer@rivosinc.com>

	* config/riscv/riscv.h (REGISTER_NAMES): Add vxsat.

2024-03-27  Segher Boessenkool  <segher@kernel.crashing.org>

	PR rtl-optimization/101523
	* combine.cc (try_combine): Don't do a 2-insn combination if
	it does not in fact change I2.

2024-03-27  Jakub Jelinek  <jakub@redhat.com>

	* doc/invoke.texi (Spec Files): Use @var{S} instead of S,
	@var{X} instead of X etc. for other placeholders.

2024-03-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114057
	* tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Mark
	BB reduction remain defs as scalar uses.

2024-03-27  Victor Do Nascimento  <victor.donascimento@arm.com>

	* config/aarch64/aarch64-option-extensions.def (rcpc3):
	Fix FEATURE_STRING field to "lrcpc3".

2024-03-27  Victor Do Nascimento  <victor.donascimento@arm.com>

	* config/aarch64/aarch64-option-extensions.def: Add LSE128
	AARCH64_OPT_EXTENSION, adding it as a dependency for the D128
	feature.
	* doc/invoke.texi (AArch64 Options): Document +lse128.

2024-03-26  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64-feature-deps.h: Use constexpr for
	out-of-line statics.

2024-03-26  Cupertino Miranda  <cupertino.miranda@oracle.com>

	PR target/114431
	* btfout.cc (get_name_for_datasec_entry): Add function.
	(btf_asm_datasec_entry): Print label when possible.

2024-03-26  Richard Ball  <richard.ball@arm.com>

	PR target/114272
	* config/aarch64/aarch64-cores.def (AARCH64_CORE):
	Change SCHEDULER_IDENT from cortexa55 to cortexa53
	for Cortex-A510 and Cortex-A520.

2024-03-26  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/111151
	* fold-const.cc (extract_muldiv_1) <case MAX_EXPR>: Punt for
	MULT_EXPR altogether, or for MAX_EXPR if c is -1.

2024-03-26  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/111736
	* tsan.cc (instrument_expr): Punt on non-generic address space
	accesses.

2024-03-26  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114471
	* tree-vect-stmts.cc (vectorizable_operation): Verify operand
	types are compatible with the result type.

2024-03-26  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114464
	* tree-vect-loop.cc (vectorizable_recurr): Verify the latch
	vector type is compatible with what we chose for the recurrence.

2024-03-26  Jakub Jelinek  <jakub@redhat.com>

	* cfgloopmanip.cc (update_loop_exit_probability_scale_dom_bbs):
	Fix comment typo - multple -> multiple.
	* config/i386/x86-tune.def (X86_TUNE_ACCUMULATE_OUTGOING_ARGS):
	Likewise.

2024-03-26  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
	__mips_strict_alignment if STRICT_ALIGNMENT.

2024-03-25  Richard Biener  <rguenther@suse.de>

	* config.gcc (amdgcn): Add gfx1036 entries.
	* config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
	(gcn_local_sym_hash): Likewise.
	* config/gcn/gcn-opts.h (enum processor_type): Likewise.
	(TARGET_GFX1036): New macro.
	* config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
	(gcn_omp_device_kind_arch_isa): Likewise.
	(output_file_start): Likewise.
	* config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
	(TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
	* config/gcn/gcn.opt: Add gfx1036.
	* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
	(main): Handle gfx1036.
	* config/gcn/t-omp-device: Add gfx1036 isa.
	* doc/install.texi (amdgcn): Add gfx1036.
	* doc/invoke.texi (-march): Likewise.

2024-03-25  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
	when V is disabled and init the RVV types and intrinic APIs.
	* config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
	error if V ext is disabled.
	* config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
	Ditto.
	(riscv_arguments_is_vector_type_p): Ditto.
	(riscv_vector_cc_function_p): Ditto.
	* config/riscv/riscv_vector.h: Remove error if V is disable.

2024-03-23  John David Anglin  <danglin@gcc.gnu.org>

	* config/pa/pa.cc (pa_output_global_address): Handle
	UNSPEC_DLTIND14R addresses.
	* config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
	UNSPEC_DLTIND14R address.

2024-03-23  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114433
	* gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
	m_bitfld_load check save_first rather than m_first.

2024-03-23  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114425
	* gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
	_Complex large/huge _BitInt types like the large/huge _BitInt types.

2024-03-23  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/111683
	* tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
	and comp_step is RS_NONZERO, return false if any reference in the
	component doesn't have DR_STEP a multiple of access size.

2024-03-23  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

	* config/xtensa/xtensa.md: Add new split pattern described above.

2024-03-22  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
	for deprecated SIGNAL and INTERRUPT usage without respective header.

2024-03-22  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
	(atomic_load<mode>): Adjust RDNA cache settings.
	(atomic_store<mode>): Likewise.
	(atomic_exchange<mode>): Likewise.

2024-03-22  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
	RDNA devices.

2024-03-22  Andrew Stubbs  <ams@baylibre.com>

	* config.gcc (amdgcn): Add gfx1103 entries.
	* config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
	(gcn_local_sym_hash): Likewise.
	* config/gcn/gcn-opts.h (enum processor_type): Likewise.
	(TARGET_GFX1103): New macro.
	* config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
	(gcn_omp_device_kind_arch_isa): Likewise.
	(output_file_start): Likewise.
	(gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
	* config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
	* config/gcn/gcn.opt: Add gfx1103.
	* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
	(main): Handle gfx1103.
	* config/gcn/t-omp-device: Add gfx1103 isa.
	* doc/install.texi (amdgcn): Add gfx1103.
	* doc/invoke.texi (-march): Likewise.

2024-03-22  Andrew Stubbs  <ams@baylibre.com>

	* dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
	bitmasks.
	(do_compare_and_jump): Remove now-redundant similar code.
	* internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
	bitmasks.
	(add_mask_and_len_args): Likewise.

2024-03-22  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
	macro __riscv_v_fixed_vlen when zvl.
	* config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
	New static func to take care of the RVV types decorated by
	the attributes.

2024-03-22  Andrew Pinski  <quic_apinski@quicinc.com>

	PR c/109619
	* builtins.cc (fold_builtin_1): Use error_operand_p
	instead of checking against ERROR_MARK.
	(fold_builtin_2): Likewise.
	(fold_builtin_3): Likewise.

2024-03-22  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/111736
	* ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
	SANITIZE_NULL instrumentation for non-generic address spaces
	for which targetm.addr_space.zero_address_valid (as) is true.

2024-03-22  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114405
	* gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
	Set rprec to limb_prec rather than 0 if tprec is divisible by
	limb_prec.  In the last bf_cur handling, set rprec to (tprec + bo_bit)
	% limb_prec rather than tprec % limb_prec and use just rprec instead
	of rprec + bo_bit.  For build_bit_field_ref offset, divide
	(tprec + bo_bit) by limb_prec rather than just tprec.

2024-03-22  Christoph Müllner  <christoph.muellner@vrull.eu>

	PR target/114194
	* config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
	Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.

2024-03-22  Jeff Law  <jlaw@ventanamicro.com>

	* config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
	tie for scalable and final stack adjustment if needed.
	Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>

2024-03-22  Pan Li  <pan2.li@intel.com>

	PR target/114352
	* common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
	New struct for func decl and target name.
	(struct riscv_func_target_hasher): New hasher for hash table mapping
	from the fn_decl to fn_target_name.
	(riscv_func_decl_hash): New func to compute the hash for fn_decl.
	(riscv_func_target_hasher::hash): New func to impl hash interface.
	(riscv_func_target_hasher::equal): New func to impl equal interface.
	(riscv_cmdline_subset_list): New static var for cmdline subset list.
	(riscv_func_target_table_lazy_init): New func to lazy init the func
	target hash table.
	(riscv_func_target_get): New func to get target name from hash table.
	(riscv_func_target_put): New func to put target name into hash table.
	(riscv_func_target_remove_and_destory): New func to remove target
	info from the hash table and destory it.
	(riscv_parse_arch_string): Set the static var cmdline_subset_list.
	* config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
	var for cmdline subset list.
	(riscv_func_target_get): New func decl.
	(riscv_func_target_put): Ditto.
	(riscv_func_target_remove_and_destory): Ditto.
	* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
	Take cmdline_subset_list instead of current_subset_list when clone.
	(riscv_process_target_attr): Record the func target info to hash table.
	(riscv_option_valid_attribute_p): Add new arg tree fndel.
	* config/riscv/riscv.cc (riscv_declare_function_name): Consume the
	func target info and print the arch message.

2024-03-22  Pan Li  <pan2.li@intel.com>

	PR target/114352
	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
	Replace implied, combine and check to func finalize.
	(riscv_subset_list::finalize): New func impl to take care of
	implied, combine ext and related checks.
	* config/riscv/riscv-subset.h: Add func decl for finalize.
	* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
	Finalize the ext before return succeed.
	* config/riscv/riscv.cc (riscv_set_current_function): Reinit the
	machine mode before when set cur function.

2024-03-21  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.

2024-03-21  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.

2024-03-21  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
	device_malloc call.

2024-03-21  liuhongt  <hongtao.liu@intel.com>

	PR tree-optimization/114396
	* tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
	and true to wi::from_mpz.

2024-03-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/111736
	* asan.cc (instrument_derefs): Do not instrument accesses
	to non-generic address-spaces.

2024-03-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113727
	* tree-sra.cc (analyze_access_subtree): Do not allow
	replacements in subtrees when grp_partial_lhs.

2024-03-21  liuhongt  <hongtao.liu@intel.com>

	PR middle-end/114347
	* doc/invoke.texi: Document -fexcess-precision=16.

2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/core-builtins.cc (bpf_core_get_index): Check if
	field contains a DECL_NAME.

2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
	Add assert to validate the string is set.
	* config/bpf/core-builtins.cc (cr_final): Make string struct
	field as const.
	(process_enum_value): Correct for field type change.
	(process_type): Set access string to "0".

2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/core-builtins.cc (core_field_info): Add
	support for POINTER_PLUS_EXPR in the root of the field expression.
	(bpf_core_get_index): Likewise.
	(pack_field_expr): Make the BTF type to point to the structure
	related node, instead of its pointer type.
	(make_core_safe_access_index): Correct to new code.

2024-03-20  Xi Ruoyao  <xry111@xry111.site>

	PR target/114407
	* config/loongarch/loongarch-opts.cc (loongarch_config_target):
	Fix typo in diagnostic message, enabing -> enabling.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
	TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
	nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
	function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
	function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
	function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
	skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
	csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-20  Yury Khrustalev  <yury.khrustalev@arm.com>

	* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114365
	* gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
	a PHI node, set iv2 to its result afterwards.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	* tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
	probabbility -> probability.
	(ch_base::copy_headers): Fix comment typo: itrations -> iterations.

2024-03-20  Jakub Jelinek  <jakub@redhat.com>

	PR bootstrap/114369
	* system.h (vec_step): Define to vec_step_ when compiling
	with clang on PowerPC.

2024-03-20  demin.han  <demin.han@starfivetech.com>

	PR target/112651
	* config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
	(enum rvv_max_lmul_enum): Ditto
	(TARGET_MAX_LMUL): Ditto
	* config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
	* config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
	(costs::better_main_loop_than_p): Ditto
	* config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul

2024-03-20  Richard Biener  <rguenther@suse.de>

	PR middle-end/113396
	* tree-dfa.cc (get_ref_base_and_extent): Use index range
	bounds only if they fit within the address-range constraints
	of offset_int.

2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>

	* config/loongarch/loongarch.cc
	(loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
	UNITS_PER_FPREG macros.
	(loongarch_hard_regno_nregs): Ditto.
	(loongarch_class_max_nregs): Ditto.
	(loongarch_get_separate_components): Ditto.
	(loongarch_process_components): Ditto.
	* config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
	(UNITS_PER_HWFPVALUE): Ditto.
	(UNITS_PER_FPVALUE): Ditto.

2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>

	* config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
	of loongarch_expand_vec_cmp()'s return value.
	(vec_cmpu<ILASX:mode><mode256_i>): Ditto.
	* config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
	(vec_cmpu<ILSX:mode><mode_i>): Ditto.
	* config/loongarch/loongarch-protos.h
	(loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
	type from bool to void.
	* config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.

2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>

	* config/loongarch/loongarch-protos.h
	(loongarch_cfun_has_cprestore_slot_p): Delete.
	(loongarch_adjust_insn_length): Delete.
	(current_section_name): Delete.
	(loongarch_split_symbol_type): Delete.
	* config/loongarch/loongarch.cc
	(loongarch_case_values_threshold): Delete.
	(loongarch_spill_class): Delete.
	(TARGET_OPTAB_SUPPORTED_P): Delete.
	(TARGET_CASE_VALUES_THRESHOLD): Delete.
	(TARGET_SPILL_CLASS): Delete.

2024-03-20  Lewis Hyatt  <lhyatt@gmail.com>

	PR c++/111918
	* diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
	* diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
	Make use of DK_ANY to indicate a diagnostic was initially enabled.
	(diagnostic_context::diagnostic_enabled): Do not change the type of
	a diagnostic if the saved classification is type DK_ANY.

2024-03-19  Martin Jambor  <mjambor@suse.cz>

	PR ipa/108802
	PR ipa/114254
	* ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
	at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
	a pointer parameter.
	(ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
	parameter, also recognize the case when pfn pointer is loaded in its
	own BB.

2024-03-19  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/99829
	* lra-constraints.cc (lra_constraints): Prevent removing insn
	with reverse equivalence to memory if the memory was reloaded.

2024-03-19  David Malcolm  <dmalcolm@redhat.com>

	PR middle-end/114348
	* diagnostic-format-json.cc
	(json_stderr_output_format::machine_readable_stderr_p): New.
	(json_file_output_format::machine_readable_stderr_p): New.
	* diagnostic-format-sarif.cc
	(sarif_stream_output_format::machine_readable_stderr_p): New.
	(sarif_file_output_format::machine_readable_stderr_p): New.
	* diagnostic.cc (diagnostic_context::action_after_output): Move
	"fnotice" to before "finish" call, so that we still have the
	diagnostic_context.
	(fnotice): Bail out if the user requested one of the
	machine-readable diagnostic output formats on stderr.
	* diagnostic.h
	(diagnostic_output_format::machine_readable_stderr_p): New pure
	virtual function.
	(diagnostic_text_output_format::machine_readable_stderr_p): New.
	(diagnostic_context::get_output_format): New accessor.

2024-03-19  Edwin Lu  <ewlu@rivosinc.com>

	PR target/114175
	* config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
	riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL

2024-03-19  Jonathan Wakely  <jwakely@redhat.com>

	* doc/install.texi (Prerequisites): Document use of autogen for
	libstdc++.

2024-03-19  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114151
	PR tree-optimization/114269
	PR tree-optimization/114322
	PR tree-optimization/114074
	* tree-chrec.cc (chrec_fold_multiply): Restrict the use of
	unsigned arithmetic when actual overflow on constant operands
	is observed.

2024-03-19  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
	arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-19  Xi Ruoyao  <xry111@xry111.site>

	PR target/114175
	* config/loongarch/loongarch.cc
	(loongarch_setup_incoming_varargs): Only skip
	loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
	functions if arg.type is NULL.

2024-03-19  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/114323
	* config/arm/arm-mve-builtins.cc
	(function_instance::reads_global_state_p): Take CP_READ_MEMORY
	into account.

2024-03-19  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
	function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-19  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
	rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-19  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114375
	* tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
	load permutation for masked loads but reject it when any
	such is necessary.
	* tree-vect-stmts.cc (vectorizable_load): Reject masked
	VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
	supported.

2024-03-19  Mary Bennett  <mary.bennett@embecosm.com>

	* common/config/riscv/riscv-common.cc: Create XCVbi extension
	support.
	* config/riscv/riscv.opt: Likewise.
	* config/riscv/corev.md: Implement cv_branch<mode> pattern
	for cv.beqimm and cv.bneimm.
	* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
	branch instruction pattern.
	* config/riscv/constraints.md: Implement constraints
	cv_bi_s5 - signed 5-bit immediate.
	* config/riscv/predicates.md: Implement predicate
	const_int5s_operand - signed 5 bit immediate.
	* doc/sourcebuild.texi: Add XCVbi documentation.

2024-03-19  Chen Jiawei  <jiawei@iscas.ac.cn>

	* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
	(RISCV_CORE): Ditto.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
	option.
	* config/riscv/riscv.cc: New def.
	* config/riscv/riscv.md: New include.
	* config/riscv/xiangshan.md: New file.

2024-03-18  David Malcolm  <dmalcolm@redhat.com>

	PR analyzer/110902
	PR analyzer/110928
	PR analyzer/111305
	PR analyzer/111441
	* selftest.h (ASSERT_NE_AT): New macro.

2024-03-18  Uros Bizjak  <ubizjak@gmail.com>

	PR target/111822
	* config/i386/i386-features.cc (smode_convert_cst): New function
	to handle SImode, DImode and TImode immediates, generalized from
	timode_convert_cst.
	(timode_convert_cst): Remove.
	(scalar_chain::convert_op): Unify from
	general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
	(general_scalar_chain::convert_op): Remove.
	(timode_scalar_chain::convert_op): Remove.
	(timode_scalar_chain::convert_insn): Update the call to
	renamed timode_convert_cst.
	* config/i386/i386-features.h (class scalar_chain):
	Redeclare convert_op as protected class member.
	(class general_calar_chain): Remove convert_op.
	(class timode_scalar_chain): Ditto.

2024-03-18  Jan Hubicka  <jh@suse.cz>

	* config/i386/zn4zn5.md: Add file missed in the previous commit.

2024-03-18  Jan Hubicka  <jh@suse.cz>
	    Karthiban Anbazhagan  <Karthiban.Anbazhagan@amd.com>

	* common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
	* common/config/i386/i386-common.cc (processor_names): Add znver5.
	(processor_alias_table): Likewise.
	* common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
	family.
	(processor_subtypes): Add znver5.
	* config.gcc (x86_64-*-* |...): Likewise.
	* config/i386/driver-i386.cc (host_detect_local_cpu): Let
	march=native detect znver5 cpu's.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Add
	znver5.
	* config/i386/i386-options.cc (m_ZNVER5): New definition
	(processor_cost_table): Add znver5.
	* config/i386/i386.cc (ix86_reassociation_width): Likewise.
	* config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
	(PTA_ZNVER5): New definition.
	* config/i386/i386.md (define_attr "cpu"): Add znver5.
	(Scheduling descriptions) Add znver5.md.
	* config/i386/x86-tune-costs.h (znver5_cost): New definition.
	* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
	(ix86_adjust_cost): Likewise.
	* config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
	(avx512_store_by_pieces): Add m_ZNVER5.
	* doc/extend.texi: Add znver5.
	* doc/invoke.texi: Likewise.
	* config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.

2024-03-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/constraints.md (CX2, CX3, CX4): New constraints.
	* config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
	* config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
	* config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
	(xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
	(xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.

2024-03-18  liuhongt  <hongtao.liu@intel.com>

	PR target/114334
	* config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
	(MODEF248): New mode iterator.
	(ssevecmodesuffix): Hanlde BF and HF.
	* config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
	(<code><mode>3): Ditto.

2024-03-18  John David Anglin  <danglin@gcc.gnu.org>

	PR rtl-optimization/112415
	* config/pa/pa.cc (pa_emit_move_sequence): Revise condition
	for symbolic memory operands.
	(pa_legitimate_address_p): Revise LO_SUM condition.
	* config/pa/pa.h (INT14_OK_STRICT): Revise define.  Move
	comment about GNU linker to predicates.md.
	* config/pa/predicates.md (floating_point_store_memory_operand):
	Revise condition for symbolic memory operands.  Update
	comment.

2024-03-17  John David Anglin  <danglin@gcc.gnu.org>

	* config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.

2024-03-16  Jakub Jelinek  <jakub@redhat.com>

	PR target/114175
	* config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
	ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
	if arg.type is NULL.

2024-03-16  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114329
	* gimple-lower-bitint.cc (struct bitint_large_huge): Declare
	build_bit_field_ref method.
	(bitint_large_huge::build_bit_field_ref): New method.
	(bitint_large_huge::lower_mergeable_stmt): Use it.

2024-03-15  YunQiang Su  <syq@gcc.gnu.org>

	* config/riscv/riscv.opt.urls: Regenerated.
	* config/rs6000/sysv4.opt.urls: Likewise.
	* config/xtensa/xtensa.opt.urls: Likewise.

2024-03-15  Jakub Jelinek  <jakub@redhat.com>

	* lower-subreg.cc (resolve_simple_move): Fix comment typo,
	betwee -> between.
	* edit-context.cc (class line_event): Fix comment typo,
	betweeen -> between.

2024-03-15  Jakub Jelinek  <jakub@redhat.com>

	PR target/114339
	* config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
	a pasto, compare code against LE rather than GE.

2024-03-15  Joe Ramsay  <Joe.Ramsay@arm.com>

	* match.pd: Fix truncation pattern for -fno-signed-zeroes

2024-03-15  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114332
	* expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.

2024-03-15  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113466
	* gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
	member.
	(bitint_large_huge::bitint_large_huge): Initialize it.
	(bitint_large_huge::~bitint_large_huge): Release it.
	(bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
	before which at least one statement has been inserted.
	(gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
	calls to a different block and add corresponding PHIs.

2024-03-15  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.opt: Support -mstrict-align, and use
	TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
	as alias.
	* config/mips/mips.h: Use TARGET_STRICT_ALIGN.
	* config/mips/mips.opt.urls: Regenerate.
	* doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.

2024-03-15  Tejas Belagod  <tejas.belagod@arm.com>

	PR middle-end/114108
	* tree-vect-patterns.cc (vect_recog_abd_pattern): Call
	vect_convert_output with the correct vecitype.

2024-03-15  Chenghui Pan  <panchenghui@loongson.cn>

	* config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
	Remove masking of operand 3.

2024-03-14  Jason Merrill  <jason@redhat.com>

	* tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
	comments.

2024-03-14  John David Anglin  <danglin@gcc.gnu.org>

	PR target/114288
	* config/pa/pa.cc (pa_legitimate_address_p): Don't allow
	14-bit displacements before reload for modes that may use
	a floating-point load or store.

2024-03-14  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf.h (INT8_TYPE): Change to signed char.

2024-03-14  Max Filippov  <jcmvbkbc@gmail.com>

	* config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
	patterns ahead of the l32i.n and s32i.n.

2024-03-14  Jakub Jelinek  <jakub@redhat.com>

	* config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.

2024-03-14  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113907
	* ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
	SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
	functions.

2024-03-14  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md (any_ge): Remove.
	(sge<u>_<X:mode><GPR:mode>): Remove.

2024-03-14  Jakub Jelinek  <jakub@redhat.com>

	PR target/114310
	* config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
	TImode force newval into a register.

2024-03-14  Chung-Lin Tang  <cltang@baylibre.com>

	* tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
	(OMP_CLAUSE__CACHE__READONLY): New macro.
	* tree-core.h (struct GTY(()) tree_base): Adjust comments for new
	uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
	OMP_CLAUSE__CACHE__READONLY.
	* tree-pretty-print.cc (dump_omp_clause): Add support for printing
	OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.

2024-03-14  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/s390/s390.cc (s390_encode_section_info): Adjust the check
	for misaligned symbols.
	* config/s390/s390.opt: Improve documentation.

2024-03-14  Jakub Jelinek  <jakub@redhat.com>

	* gimple-iterator.cc (edge_before_returns_twice_call): Copy all
	flags and probability from ad_edge to e edge.  If CDI_DOMINATORS
	are computed, recompute immediate dominator of other_edge->src
	and other_edge->dest.
	(gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
	for the returns_twice call case to the gsi_for_stmt (stmt) to deal
	with update it for bb splitting.

2024-03-14  liuhongt  <hongtao.liu@intel.com>

	* config/i386/i386-features.cc
	(general_scalar_chain::convert_op): Handle REG_EH_REGION note.
	(convert_scalars_to_vector): Ditto.
	* config/i386/i386-features.h (class scalar_chain): New
	memeber control_flow_insns.

2024-03-13  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114319
	* gimple-ssa-store-merging.cc
	(imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
	allow matching __builtin_bswap64 if there is bswapsi2 optab.

2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* config/s390/s390.cc (s390_secondary_reload): Guard
	SYMBOL_FLAG_NOTALIGN2_P.

2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* config/s390/s390-builtin-types.def: Update to reflect latest
	changes.
	* config/s390/s390-builtins.def: Streamline vector builtins with
	LLVM.

2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* config/s390/s390-builtins.def (vec_permi): Deprecate.
	(vec_ctd): Deprecate.
	(vec_ctd_s64): Deprecate.
	(vec_ctd_u64): Deprecate.
	(vec_ctsl): Deprecate.
	(vec_ctul): Deprecate.
	(vec_ld2f): Deprecate.
	(vec_st2f): Deprecate.
	(vec_insert): Deprecate overloads with bool vectors.

2024-03-13  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114313
	* gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
	TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
	(bitint_large_huge::handle_load): Pass NULL_TREE rather than
	rhs_type to limb_access for the bitfield load cases.
	(bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
	lhs_type to limb_access if nlhs is non-NULL.

2024-03-13  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/112709
	* asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
	build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
	gsi_safe_insert_before instead of gsi_insert_before.

2024-03-13  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/112709
	* gimple-iterator.h (gsi_safe_insert_before,
	gsi_safe_insert_seq_before): Declare.
	* gimple-iterator.cc: Include gimplify.h.
	(edge_before_returns_twice_call, adjust_before_returns_twice_call,
	gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
	* ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
	instrument_nonnull_arg, instrument_nonnull_return): Use
	gsi_safe_insert_before instead of gsi_insert_before.
	(maybe_instrument_pointer_overflow): Use force_gimple_operand,
	gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
	instead of force_gimple_operand_gsi.
	(instrument_object_size): Likewise.  Use gsi_safe_insert_before
	instead of gsi_insert_before.

2024-03-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114121
	* tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
	converted operand properly.
	(chrec_fold_multiply): Likewise.  Handle missed recursion.

2024-03-12  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/112709
	* asan.cc (has_stmt_been_instrumented_p): Don't instrument call
	stores on the caller side unless it is a call to a builtin or
	internal function or function doesn't return by hidden reference.
	(maybe_instrument_call): Likewise.
	(instrument_derefs): Instrument stores to RESULT_DECL if
	returning by hidden reference.

2024-03-12  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114293
	* tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
	max is smaller than min, set max to ~(size_t)0.

2024-03-12  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
	code style greater than 80 chars.
	(riscv_cpu_cpp_builtins): Fix useless empty line, indent
	with 3 space(s) and argument unalignment.

2024-03-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114297
	* tree-vect-loop.cc (vectorizable_live_operation): Pass in the
	live stmts SLP node to vect_create_epilog_for_reduction.

2024-03-12  Andrew Pinski  <quic_apinski@quicinc.com>

	PR driver/114314
	* common.opt (fmultiflags): Add RejectNegative.

2024-03-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
	* config/aarch64/aarch64.opt: Likewise.
	* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
	* config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
	(aarch64_expand_epilogue): Likewise.
	(aarch64_post_cfi_startproc): Likewise.
	(aarch64_handle_no_branch_protection): Copy and rename.
	(aarch64_handle_standard_branch_protection): Likewise.
	(aarch64_handle_pac_ret_protection): Likewise.
	(aarch64_handle_pac_ret_leaf): Likewise.
	(aarch64_handle_pac_ret_b_key): Likewise.
	(aarch64_handle_bti_protection): Likewise.
	(aarch64_override_options): Update branch protection validation.
	(aarch64_handle_attr_branch_protection): Likewise.
	* config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
	Pass branch protection type description as argument.
	(struct aarch_branch_protect_type): Move from aarch-common.h.
	* config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
	Remove.
	(aarch_handle_standard_branch_protection): Remove.
	(aarch_handle_pac_ret_protection): Remove.
	(aarch_handle_pac_ret_leaf): Remove.
	(aarch_handle_pac_ret_b_key): Remove.
	(aarch_handle_bti_protection): Remove.
	(aarch_validate_mbranch_protection): Pass branch protection type
	description as argument.
	* config/arm/aarch-common.h (enum aarch_key_type): Remove.
	(struct aarch_branch_protect_type): Remove.
	* config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
	* config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
	(arm_handle_standard_branch_protection): Likewise.
	(arm_handle_pac_ret_protection): Likewise.
	(arm_handle_pac_ret_leaf): Likewise.
	(arm_handle_bti_protection): Likewise.
	(arm_configure_build_target): Update branch protection validation.
	* config/arm/arm.opt: Remove aarch_ra_sign_key.

2024-03-11  Richard Biener  <rguenther@suse.de>

	PR middle-end/114299
	* gimplify.cc (internal_get_tmp_var): When gimplification
	of VAL failed, return a decl.

2024-03-11  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114278
	* tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
	longer addressable, set DECL_NOT_GIMPLE_REG_P on them.

2024-03-11  Eric Botcazou  <ebotcazou@adacore.com>

	PR debug/113519
	PR debug/113777
	* dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
	generate the DIE with the same parent as in the regular case.

2024-03-11  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/95351
	* fold-const.cc (merge_truthop_with_opposite_arm): Use
	the type of the operands of the comparison and not the type
	of the comparison.

2024-03-10  jlaw  <jeffreyalaw@gmail.com>

	PR tree-optimization/110199
	* tree-ssa-scopedtables.cc
	(avail_exprs_stack::simplify_binary_operation): Generalize handling
	of MIN_EXPR/MAX_EXPR to allow additional simplifications.  Canonicalize
	comparison operands for other cases.

2024-03-10  Pan Li  <pan2.li@intel.com>

	* tree-vect-stmts.cc (vectorizable_store): Enable the assert
	during transform process.
	(vectorizable_load): Ditto.

2024-03-10  jlaw  <jeffreyalaw@gmail.com>

	PR target/102250
	* doc/install.texi: Document need for python when building
	RISC-V compilers.

2024-03-10  jlaw  <jeffreyalaw@gmail.com>

	PR target/111362
	* mode-switching.cc (optimize_mode_switching): Only process
	NONDEBUG insns.

2024-03-09  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.md: Fix typos in comment, indentation glitches
	and some other nits.

2024-03-09  Jakub Jelinek  <jakub@redhat.com>

	PR target/114284
	* fwprop.cc (try_fwprop_subst_pattern): Don't propagate
	src containing MEMs unless prop.likely_profitable_p ().

2024-03-09  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
	Support 'Q' for R_LARCH_RELAX for TLS IE.
	(loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
	IE.
	* config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.

2024-03-09  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
	usum_widenqihi and add_zero_extend1.
	[MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
	sub+sign_extend.
	* config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
	Compute exact insn lengths.
	(*usum_widenqihi3): Allow input operands to commute.

2024-03-09  Jakub Jelinek  <jakub@redhat.com>

	* config/i386/i386.opt.urls: Regenerate.

2024-03-09  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/sync.md (atomic_cas_value_strong<mode>):
	In loongarch64, a sign extension operation is added when
	operands[2] is a register operand and the mode is SImode.

2024-03-08  Martin Jambor  <mjambor@suse.cz>

	PR ipa/113757
	* tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
	id->killed_new_ssa_names.

2024-03-08  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/113790
	* lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
	for non-reload pseudo too.

2024-03-08  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
	not attempt inline expansion if size is above threshold.
	* config/bpf/bpf.opt (-minline-memops-threshold): New option.
	* doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
	Document.

2024-03-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114269
	PR tree-optimization/114074
	* tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
	in the third CASE_CONVERT case as well.
	(chrec_fold_multiply): Handle sign-conversions from unsigned
	by performing the operation in the unsigned type.

2024-03-08  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
	* config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.

2024-03-08  Jakub Jelinek  <jakub@redhat.com>

	* bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
	asm_noperands < 0 means it is not asm goto too.

2024-03-08  Jakub Jelinek  <jakub@redhat.com>

	PR target/38534
	* config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
	option.
	* config/i386/i386-options.cc (ix86_set_func_type): Don't use
	TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
	ix86_noreturn_no_callee_saved_registers is enabled.
	* doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.

2024-03-08  Jakub Jelinek  <jakub@redhat.com>

	PR debug/113918
	* dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
	on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.

2024-03-08  demin.han  <demin.han@starfivetech.com>

	PR target/114264
	* config/riscv/riscv-vector-costs.cc: Fix ICE

2024-03-08  Haochen Gui  <guihaoc@gcc.gnu.org>

	* fwprop.cc (forward_propagate_into): Return false for volatile set
	source rtx.

2024-03-07  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	PR target/113618
	* config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
	(aarch64_expand_cpymem): Emit single load/store only.
	(aarch64_set_one_block): Emit single stores only.

2024-03-07  Robin Dapp  <rdapp@ventanamicro.com>

	PR middle-end/114196
	* tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
	vectorization guards.

2024-03-07  Jonathan Wakely  <jwakely@redhat.com>

	* doc/cppopts.texi: Remove incorrect claim about -dD not
	outputting predefined macros.

2024-03-07  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>

	PR target/113950
	* config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
	and simplify else if with else.

2024-03-07  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>

	* system.h: Include safe-ctype.h after C++ standard headers.

2024-03-07  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/110079
	* bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
	asm goto.

2024-03-07  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/105533
	* expmed.cc (choose_mult_variant): Only try the val - 1 variant
	if val is not HOST_WIDE_INT_MIN or if mode has exactly
	HOST_BITS_PER_WIDE_INT precision.  Avoid triggering UB while computing
	val - 1.

2024-03-07  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/105533
	* tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
	Multiple op->off by BITS_PER_UNIT instead of shifting it left by
	LOG2_BITS_PER_UNIT.

2024-03-07  Yang Yujie  <yangyujie@loongson.cn>

	* config.gcc: Add a case for loongarch*-*-linux-musl*.
	* config/loongarch/linux.h: Disable the multilib-compatible
	treatment for *musl* targets.
	* config/loongarch/musl.h: New file.

2024-03-07  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114009
	* genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
	argument even for GENERIC, not just for GIMPLE.
	* match.pd (a * !a -> 0): New simplifications.

2024-03-07  demin.han  <demin.han@starfivetech.com>

	* config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
	* config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
	(expand_vec_cmp_float): Adapt arguments

2024-03-06  Uros Bizjak  <ubizjak@gmail.com>

	PR target/114232
	* config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
	of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
	(negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
	(<plusminus:insn>v2qi3): Enable for optimize_size instead
	of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
	(<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
	(<any_shift:insn>v2qi3): Enable for optimize_size instead
	of optimize_function_for_size_p.

2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>

	PR target/114200
	PR target/114202
	* config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.

2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>

	* config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
	(costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
	offset handling.
	(costs::add_stmt_cost): Also adjust cost for statements without
	stmt_info.
	* config/riscv/riscv-vector-costs.h: Define zero constant.

2024-03-06  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	PR target/113915
	* config/arm/arm.md (NOCOND): Improve comment.
	(arm_rev*) Add predicable.
	* config/arm/arm.cc (arm_final_prescan_insn): Add check for
	PREDICABLE_YES.

2024-03-06  Jeff Law  <jlaw@ventanamicro.com>

	PR target/113001
	PR target/112871
	* config/riscv/riscv.cc (expand_conditional_move): Do not swap
	operands when the comparison operand is the same as the false
	arm for a NE test.

2024-03-06  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
	Eliminate common code and use generic code instead.

2024-03-06  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
	rtx cost.

2024-03-06  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114239
	* tree-vect-loop.cc (vect_get_vect_def): Remove.
	(vect_create_epilog_for_reduction): The passed in stmt_info
	should now be the live stmt that produces the scalar reduction
	result.  Revert PR114192 fix.  Base reduction info off
	info_for_reduction.  Remove special handling of
	early-break/peeled, restore original vector def gathering.
	Make sure to pick the correct exit PHIs.
	(vectorizable_live_operation): Pass in the proper stmt_info
	for early break exits.

2024-03-06  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
	out-of-class definitions of static constants.

2024-03-06  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114249
	* tree-vect-slp.cc (vect_build_slp_instance): Move making
	a BB reduction lane number even ...
	(vect_slp_check_for_roots): ... here to avoid leaking
	pattern defs.

2024-03-06  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114246
	* tree-ssa-dse.cc (increment_start_addr): Strip useless
	type conversions from the adjusted address.

2024-03-06  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/114190
	* config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
	Call df_remove_problem for df_note before calling df_analyze.

2024-03-05  Cupertino Miranda  <cupertino.miranda@oracle.com>
	    Indu Bhagat  <indu.bhagat@oracle.com>

	PR debug/114186
	* dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
	in the correct order of the dimensions.
	(gen_ctf_subrange_type): Refactor out handling of
	DW_TAG_subrange_type DIE to here.

2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>

	PR sanitizer/97696
	* asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.

2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
	and luti_strided.
	* config/aarch64/aarch64-sme.md
	(@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
	(@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
	(@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
	* config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
	(early_ra::maybe_convert_to_strided_access): Remove support for
	strided LUTI2 and LUTI4.

2024-03-05  Richard Earnshaw  <rearnsha@arm.com>

	PR target/113510
	* config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
	low_register_operand.

2024-03-05  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
	in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
	to "X = Y, X o= CST".

2024-03-05  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
	s9 as an alias of r22.

2024-03-05  Roger Sayle  <roger@nextmovesoftware.com>

	* config/avr/avr-protos.h (avr_out_insv): New proto.
	* config/avr/avr.cc (avr_out_insv): New function.
	(avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
	(avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
	* config/avr/avr.md (define_attr "adjust_len") Add insv.
	(andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
	Add constraint alternative where the 3rd operand is a power
	of 2, and the source register may differ from the destination.
	(*insv.any_shift.<mode>_split): Call avr_out_insv to output
	instructions.  Set attr "length" to "insv".
	* config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.

2024-03-05  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114231
	* tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
	processing a BB SLP root.

2024-03-05  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/114211
	* lower-subreg.cc (resolve_simple_move): For double-word
	rotates by BITS_PER_WORD if there is overlap between source
	and destination use a temporary.

2024-03-05  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114157
	* gimple-lower-bitint.cc: Include stor-layout.h.
	(mergeable_op): Return true for BIT_FIELD_REF.
	(struct bitint_large_huge): Declare handle_bit_field_ref method.
	(bitint_large_huge::handle_bit_field_ref): New method.
	(bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.

2024-03-05  Jakub Jelinek  <jakub@redhat.com>

	PR target/114116
	* config/i386/i386.h (enum call_saved_registers_type): Add
	TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
	* config/i386/i386-options.cc (ix86_set_func_type): Remove
	has_no_callee_saved_registers variable, add no_callee_saved_registers
	instead, initialize it depending on whether it is
	no_callee_saved_registers function or not.  Don't set it if
	no_caller_saved_registers attribute is present.  Adjust users.
	* config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
	TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
	TYPE_NO_CALLEE_SAVED_REGISTERS.
	(ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.

2024-03-05  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
	mode_size related code.

2024-03-05  Patrick Palka  <ppalka@redhat.com>

	* doc/invoke.texi (-Wno-global-module): Document.

2024-03-04  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
	* config/bpf/bpf.cc (bpf_expand_setmem): New.
	* config/bpf/bpf.md (setmemdi): New define_expand.

2024-03-04  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/113010
	* combine.cc (simplify_comparison): Guard the
	WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
	and initialize inner_mode.

2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
	VMLALDAVAXQ_U cases.
	(VMLALDAVXQ): Remove iterator.
	(VMLALDAVXQ_P): Likewise.
	(VMLALDAVAXQ): Likewise.
	* config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
	mode iterator attribute with V4BI mode.
	* config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
	VMLALDAVAXQ_U): Remove unused unspecs.

2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
	* config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
	attribute.
	* config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
	vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
	vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
	vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
	vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
	vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
	vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
	vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
	vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
	vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.

2024-03-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	* config/arm/arm.md (mve_unpredicated_insn): New attribute.
	* config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
	(MVE_VPT_UNPREDICATED_INSN_P): Likewise.
	(MVE_VPT_PREDICABLE_INSN_P): Likewise.
	* config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
	* config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
	(arm_vcx1q<a>v16qi): Likewise.
	(arm_vcx1qav16qi): Likewise.
	(arm_vcx1qv16qi): Likewise.
	(arm_vcx2q<a>_p_v16qi): Likewise.
	(arm_vcx2q<a>v16qi): Likewise.
	(arm_vcx2qav16qi): Likewise.
	(arm_vcx2qv16qi): Likewise.
	(arm_vcx3q<a>_p_v16qi): Likewise.
	(arm_vcx3q<a>v16qi): Likewise.
	(arm_vcx3qav16qi): Likewise.
	(arm_vcx3qv16qi): Likewise.
	(@mve_<mve_insn>q_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_int_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_<supf>v4si): Likewise.
	(@mve_<mve_insn>q_n_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_r_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_f<mode>): Likewise.
	(@mve_<mve_insn>q_m_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_m_f<mode>): Likewise.
	(@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
	(@mve_<mve_insn>q_p_<supf>v4si): Likewise.
	(@mve_<mve_insn>q_p_<supf><mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
	(@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
	(mve_v<absneg_str>q_f<mode>): Likewise.
	(mve_<mve_addsubmul>q<mode>): Likewise.
	(mve_<mve_addsubmul>q_f<mode>): Likewise.
	(mve_vadciq_<supf>v4si): Likewise.
	(mve_vadciq_m_<supf>v4si): Likewise.
	(mve_vadcq_<supf>v4si): Likewise.
	(mve_vadcq_m_<supf>v4si): Likewise.
	(mve_vandq_<supf><mode>): Likewise.
	(mve_vandq_f<mode>): Likewise.
	(mve_vandq_m_<supf><mode>): Likewise.
	(mve_vandq_m_f<mode>): Likewise.
	(mve_vandq_s<mode>): Likewise.
	(mve_vandq_u<mode>): Likewise.
	(mve_vbicq_<supf><mode>): Likewise.
	(mve_vbicq_f<mode>): Likewise.
	(mve_vbicq_m_<supf><mode>): Likewise.
	(mve_vbicq_m_f<mode>): Likewise.
	(mve_vbicq_m_n_<supf><mode>): Likewise.
	(mve_vbicq_n_<supf><mode>): Likewise.
	(mve_vbicq_s<mode>): Likewise.
	(mve_vbicq_u<mode>): Likewise.
	(@mve_vclzq_s<mode>): Likewise.
	(mve_vclzq_u<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
	(@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
	(mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
	(mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
	(mve_vcvtaq_<supf><mode>): Likewise.
	(mve_vcvtaq_m_<supf><mode>): Likewise.
	(mve_vcvtbq_f16_f32v8hf): Likewise.
	(mve_vcvtbq_f32_f16v4sf): Likewise.
	(mve_vcvtbq_m_f16_f32v8hf): Likewise.
	(mve_vcvtbq_m_f32_f16v4sf): Likewise.
	(mve_vcvtmq_<supf><mode>): Likewise.
	(mve_vcvtmq_m_<supf><mode>): Likewise.
	(mve_vcvtnq_<supf><mode>): Likewise.
	(mve_vcvtnq_m_<supf><mode>): Likewise.
	(mve_vcvtpq_<supf><mode>): Likewise.
	(mve_vcvtpq_m_<supf><mode>): Likewise.
	(mve_vcvtq_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
	(mve_vcvtq_m_to_f_<supf><mode>): Likewise.
	(mve_vcvtq_n_from_f_<supf><mode>): Likewise.
	(mve_vcvtq_n_to_f_<supf><mode>): Likewise.
	(mve_vcvtq_to_f_<supf><mode>): Likewise.
	(mve_vcvttq_f16_f32v8hf): Likewise.
	(mve_vcvttq_f32_f16v4sf): Likewise.
	(mve_vcvttq_m_f16_f32v8hf): Likewise.
	(mve_vcvttq_m_f32_f16v4sf): Likewise.
	(mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
	(mve_vdwdupq_wb_u<mode>_insn): Likewise.
	(mve_veorq_s><mode>): Likewise.
	(mve_veorq_u><mode>): Likewise.
	(mve_veorq_f<mode>): Likewise.
	(mve_vidupq_m_wb_u<mode>_insn): Likewise.
	(mve_vidupq_u<mode>_insn): Likewise.
	(mve_viwdupq_m_wb_u<mode>_insn): Likewise.
	(mve_viwdupq_wb_u<mode>_insn): Likewise.
	(mve_vldrbq_<supf><mode>): Likewise.
	(mve_vldrbq_gather_offset_<supf><mode>): Likewise.
	(mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
	(mve_vldrbq_z_<supf><mode>): Likewise.
	(mve_vldrdq_gather_base_<supf>v2di): Likewise.
	(mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
	(mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
	(mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
	(mve_vldrdq_gather_offset_<supf>v2di): Likewise.
	(mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
	(mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
	(mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
	(mve_vldrhq_<supf><mode>): Likewise.
	(mve_vldrhq_fv8hf): Likewise.
	(mve_vldrhq_gather_offset_<supf><mode>): Likewise.
	(mve_vldrhq_gather_offset_fv8hf): Likewise.
	(mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
	(mve_vldrhq_gather_offset_z_fv8hf): Likewise.
	(mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
	(mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
	(mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
	(mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
	(mve_vldrhq_z_<supf><mode>): Likewise.
	(mve_vldrhq_z_fv8hf): Likewise.
	(mve_vldrwq_<supf>v4si): Likewise.
	(mve_vldrwq_fv4sf): Likewise.
	(mve_vldrwq_gather_base_<supf>v4si): Likewise.
	(mve_vldrwq_gather_base_fv4sf): Likewise.
	(mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
	(mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
	(mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
	(mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
	(mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
	(mve_vldrwq_gather_base_z_fv4sf): Likewise.
	(mve_vldrwq_gather_offset_<supf>v4si): Likewise.
	(mve_vldrwq_gather_offset_fv4sf): Likewise.
	(mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
	(mve_vldrwq_gather_offset_z_fv4sf): Likewise.
	(mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
	(mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
	(mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
	(mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
	(mve_vldrwq_z_<supf>v4si): Likewise.
	(mve_vldrwq_z_fv4sf): Likewise.
	(mve_vmvnq_s<mode>): Likewise.
	(mve_vmvnq_u<mode>): Likewise.
	(mve_vornq_<supf><mode>): Likewise.
	(mve_vornq_f<mode>): Likewise.
	(mve_vornq_m_<supf><mode>): Likewise.
	(mve_vornq_m_f<mode>): Likewise.
	(mve_vornq_s<mode>): Likewise.
	(mve_vornq_u<mode>): Likewise.
	(mve_vorrq_<supf><mode>): Likewise.
	(mve_vorrq_f<mode>): Likewise.
	(mve_vorrq_m_<supf><mode>): Likewise.
	(mve_vorrq_m_f<mode>): Likewise.
	(mve_vorrq_m_n_<supf><mode>): Likewise.
	(mve_vorrq_n_<supf><mode>): Likewise.
	(mve_vorrq_s<mode>): Likewise.
	(mve_vorrq_s<mode>): Likewise.
	(mve_vsbciq_<supf>v4si): Likewise.
	(mve_vsbciq_m_<supf>v4si): Likewise.
	(mve_vsbcq_<supf>v4si): Likewise.
	(mve_vsbcq_m_<supf>v4si): Likewise.
	(mve_vshlcq_<supf><mode>): Likewise.
	(mve_vshlcq_m_<supf><mode>): Likewise.
	(mve_vshrq_m_n_<supf><mode>): Likewise.
	(mve_vshrq_n_<supf><mode>): Likewise.
	(mve_vstrbq_<supf><mode>): Likewise.
	(mve_vstrbq_p_<supf><mode>): Likewise.
	(mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
	(mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrdq_scatter_base_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
	(mve_vstrhq_<supf><mode>): Likewise.
	(mve_vstrhq_fv8hf): Likewise.
	(mve_vstrhq_p_<supf><mode>): Likewise.
	(mve_vstrhq_p_fv8hf): Likewise.
	(mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
	(mve_vstrwq_<supf>v4si): Likewise.
	(mve_vstrwq_fv4sf): Likewise.
	(mve_vstrwq_p_<supf>v4si): Likewise.
	(mve_vstrwq_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
	(mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.

2024-03-04  Marek Polacek  <polacek@redhat.com>

	* doc/extend.texi: Update [[gnu::no_dangling]].

2024-03-04  Andrew Stubbs  <ams@baylibre.com>

	* dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
	* expr.cc (store_constructor): Likewise.
	(do_store_flag): Likewise.

2024-03-04  Mark Wielaard  <mark@klomp.org>

	* common.opt.urls: Regenerate.
	* config/avr/avr.opt.urls: Likewise.
	* config/i386/i386.opt.urls: Likewise.
	* config/pru/pru.opt.urls: Likewise.
	* config/riscv/riscv.opt.urls: Likewise.
	* config/rs6000/rs6000.opt.urls: Likewise.

2024-03-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114197
	* tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
	there are volatile bitfield accesses.
	(pass_if_conversion::execute): Throw away result if the
	if-converted and original loops are not nested as expected.

2024-03-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114164
	* tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
	the code generated for mask argument setup is not supported.

2024-03-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114203
	* tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
	adjustment before making the result defined at zero.

2024-03-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114192
	* tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
	appropriate def for the live out stmt in case of an alternate
	exit.

2024-03-04  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114209
	* gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
	unshare_expr when creating a MEM_REF from MEM_REF.
	(bitint_large_huge::lower_stmt): Call unshare_expr.

2024-03-04  Jakub Jelinek  <jakub@redhat.com>

	PR target/114184
	* config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
	is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
	register.

2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>

	PR target/114187
	* simplify-rtx.cc (simplify_context::simplify_subreg): Call
	lowpart_subreg to perform type conversion, to avoid confusion
	over the offset to use in the call to simplify_reg_subreg.

2024-03-03  Greg McGary  <gkm@rivosinc.com>

	PR rtl-optimization/113010
	* combine.cc (simplify_comparison): Simplify a SUBREG on
	WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
	MEM load.

2024-03-03  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
	Use bool in place of int for boolean logic (if possible).
	Move declarations to definitions (if possible).
	* config/avr/avr.md: Use C++ comments.  Fix some indentation glitches.
	* config/avr/avr-dimode.md: Same.
	* config/avr/constraints.md: Same.
	* config/avr/predicates.md: Same.

2024-03-03  Uros Bizjak  <ubizjak@gmail.com>

	PR target/113720
	* config/alpha/alpha.md (umuldi3_highpart): Remove expander.
	(*umuldi3_highpart_reg): Rename to umuldi3_highpart and
	simplify insn RTX using UMUL_HIGHPART rtx_code.
	(*umuldi3_highpart_const): Remove.

2024-03-03  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114100
	* config/avr/avr-protos.h (_reg_unused_after): Remove proto.
	* config/avr/avr.cc (_reg_unused_after): Make static.  And
	add 3rd argument to skip the current insn.
	(reg_unused_after): Adjust call of reg_unused_after.
	(avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
	unneeded frame pointer adjustments.

2024-03-03  Georg-Johann Lay  <avr@gjlay.de>

	PR target/92729
	* config/avr/avr.md (define_attr "cc"): Remove.
	* config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
	from prototype.
	* config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
	its uses.  Add insn argument.
	(avr_out_plus_symbol): Remove pcc argument and its uses.
	(avr_out_plus): Remove pcc argument and its uses.
	Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
	(avr_out_round): Adjust call of avr_out_plus.

2024-03-03  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
	from  r14-9273.

2024-03-03  Oleg Endo  <olegendo@gcc.gnu.org>

	PR target/101737
	* config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
	is not an insn, but e.g. a code label.

2024-03-02  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.md (REG_0, ... REG_36): New define_constants.
	* config/avr/avr.cc: Use them instead of magic numbers when it
	means a register number.

2024-03-02  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc: Adjust some comments.

2024-03-02  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114100
	* config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
	the low part of the frame pointer with 8-bit stack pointer.

2024-03-01  Patrick Palka  <ppalka@redhat.com>

	PR c++/104919
	PR c++/106009
	* tree-inline.cc (remap_decl): Handle copy_decl returning the
	original decl.
	(remap_decls): Handle remap_decl returning the original decl.
	(copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
	CONST_DECL.

2024-03-01  Jeff Law  <jlaw@ventanamicro.com>

	* config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
	type attribute.
	(extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
	(movdi_32bit, movdi_64bit, movsi_internal): Likewise.
	(movhi_internal, movqi_internal): Likewise.
	(movsf_softfloat, movsf_hardfloat): Likewise.
	(movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
	(movdf_softfloat): Likewise.

2024-03-01  Marek Polacek  <polacek@redhat.com>

	PR c++/110358
	PR c++/109642
	* doc/extend.texi: Document gnu::no_dangling.
	* doc/invoke.texi: Mention that gnu::no_dangling disables
	-Wdangling-reference.

2024-03-01  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.opt: Overhaul help screen.

2024-03-01  Jakub Jelinek  <jakub@redhat.com>
	    Tobias Burnus  <tburnus@baylibre.com>

	PR c++/110347
	* gimplify.cc (omp_notice_variable): Fix 'shared' arg to
	lang_hooks.decls.omp_disregard_value_expr for
	(first)private in target regions.

2024-03-01  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114136
	* calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
	n_named_args initially before INIT_CUMULATIVE_ARGS to
	structure_value_addr_parm rather than 0, after it don't modify
	it if strict_argument_naming and clear only if
	!pretend_outgoing_varargs_named.

2024-03-01  Jakub Jelinek  <jakub@redhat.com>

	PR debug/114015
	* dwarf2out.cc (should_move_die_to_comdat): Return false for
	aggregates without DW_AT_byte_size attribute or with non-constant
	DW_AT_byte_size.

2024-03-01  Georg-Johann Lay  <avr@gjlay.de>

	* doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
	valid values for level.

2024-03-01  Richard Biener  <rguenther@suse.de>

	PR middle-end/114070
	* match.pd ((c ? a : b) op d  -->  c ? (a op d) : (b op d)):
	Allow the folding if before lowering and the current IL
	isn't supported with vcond_mask.

2024-03-01  xuli  <xuli1@eswincomputing.com>

	* config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
	attribute to riscv_attribute_table.
	(riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
	(riscv_fntype_abi): Add riscv_vector_cc attribute check.
	* doc/extend.texi: Add riscv_vector_cc attribute description.

2024-03-01  Pan Li  <pan2.li@intel.com>

	PR target/112817
	* config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
	RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
	* config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
	(enum rvv_vector_bits_enum): New enum for different RVV vector bits.
	* config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
	comments for option replacement.
	* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
	riscv_autovec_preference to rvv_vector_bits.
	(vls_mode_valid_p): Ditto.
	(estimated_poly_value): Ditto.
	* config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
	vector chunks and honor new option mrvv-vector-bits.
	(riscv_override_options_internal): Update comments and rename the
	vector chunks.
	* config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
	internal option param=riscv-autovec-preference.

2024-03-01  Jakub Jelinek  <jakub@redhat.com>

	* function.cc (assign_parms): Only call assign_parms_setup_varargs
	early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.

2024-03-01  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114156
	* gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
	rhs1 of a VCE to have no underlying variable if it is a load and
	handle that case.

2024-02-29  David Malcolm  <dmalcolm@redhat.com>

	PR analyzer/114159
	* function.cc (function_name): Make param const.
	* function.h (function_name): Likewise.

2024-02-29  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114100
	* doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
	* config/avr/avr.opt (-mfuse-add=): New target option.
	* common/config/avr/avr-common.cc (avr_option_optimization_table)
	[OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
	[OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
	* config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
	* config/avr/avr-protos.h (avr_split_tiny_move)
	(make_avr_pass_fuse_add): New protos.
	* config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
	avr_split_tiny_move to split indirect memory accesses.
	(gen_move_clobbercc): New define_expand helper.
	* config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
	(avr_pass_fuse_add): New class from rtl_opt_pass.
	(make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
	(reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
	(avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
	of PLUS addressing for AVR_TINY.
	(avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
	(avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
	(avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.

2024-02-29  Georg-Johann Lay  <avr@gjlay.de>

	PR target/114132
	* config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
	* config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
	(avr_function_arg): Set it.
	(avr_frame_pointer_required_p): Use it instead of .nregs.

2024-02-29  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/108174
	* config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
	static and mark with GTY.

2024-02-29  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md
	(loongarch_<crc>_w_<size>_w_extended): New define_insn.

2024-02-29  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md (CRC): New define_int_iterator.
	(crc): New define_int_attr.
	(loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
	into ...
	(loongarch_<crc>_w_<size>_w): ... here.

2024-02-29  Kito Cheng  <kito.cheng@sifive.com>

	PR target/114130
	* config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
	extend the expected value if needed.

2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config.gcc (target_gtfiles): Change coreout to btfext-out.
	(extra_objs): Change coreout to btfext-out.
	* config/bpf/coreout.cc: Rename to btfext-out.cc.
	* config/bpf/btfext-out.cc: Add.
	* config/bpf/coreout.h: Rename to btfext-out.h.
	* config/bpf/btfext-out.h: Add.
	* config/bpf/core-builtins.cc: Change include.
	* config/bpf/core-builtins.h: Change include.
	* config/bpf/t-bpf: Accomodate renamed files.

2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>

	PR target/113453
	* config/bpf/bpf.cc (bpf_function_prologue): Define target
	hook.
	* config/bpf/coreout.cc (brf_ext_info_section)
	(btf_ext_info): Move from coreout.h
	(btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
	(bpf_core_reloc): Rename to btf_ext_core_reloc.
	(btf_ext): Add static variable.
	(btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
	(bpf_create_or_find_funcinfo, bpt_create_core_reloc)
	(btf_ext_add_string, btf_funcinfo_type_callback)
	(btf_add_func_info_for, btf_validate_funcinfo)
	(btf_ext_info_len, output_btfext_func_info): Add function.
	(output_btfext_header, bpf_core_reloc_add)
	(output_btfext_core_relocs, btf_ext_init, btf_ext_output):
	Change to support new structs.
	* config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
	Move and change in coreout.cc.
	(btf_add_func_info_for, btf_ext_add_string): Add prototypes.

2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
	enabled by default for BPF.
	(bpf_file_end): Call BTF deallocation.
	(bpf_asm_init_sections): Correct condition.
	* dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
	deallocation.
	(ctf_debuf_finish): Correct condition for calling
	ctf_debug_finalize.

2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
	(traverse_btf_func_types): Define function.
	* ctfc.h (funcs_traverse_callback): Typedef for function
	prototype.
	(traverse_btf_func_types): Add prototype.

2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* btfout.cc (btf_collect_dataset): Corrects BTF type id.

2024-02-28  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113831
	PR tree-optimization/108355
	* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
	PR113831 fix.

2024-02-28  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114121
	* tree-ssa-sccvn.h (vn_reference_s::offset,
	vn_reference_s::max_size): New fields.
	(vn_reference_insert_pieces): Adjust prototype.
	* tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
	* tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
	size, allow using "don't know" state.
	(vn_walk_cb_data::finish): Pass along offset/max_size.
	(vn_reference_lookup_or_insert_for_pieces): Take offset and
	max_size as argument and use it.
	(vn_reference_lookup_3): Properly adjust offset and max_size
	according to the adjusted ao_ref.
	(vn_reference_lookup_pieces): Initialize offset and max_size.
	(vn_reference_lookup): Likewise.
	(vn_reference_lookup_call): Likewise.
	(vn_reference_insert): Likewise.
	(visit_reference_op_call): Likewise.
	(vn_reference_insert_pieces): Take offset and max_size
	as argument and use it.

2024-02-28  Juergen Christ  <jchrist@linux.ibm.com>

	PR tree-optimization/114075
	* tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
	point vectors

2024-02-28  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114041
	* graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
	INTEGRAL_TYPE_P check rather than INTEGER_TYPE.

2024-02-28  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113988
	* stor-layout.h (bitwise_mode_for_size): Declare.
	* stor-layout.cc (bitwise_mode_for_size): New function.
	* gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
	Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
	Use BITS_PER_UNIT instead of 8.

2024-02-27  Uros Bizjak  <ubizjak@gmail.com>

	PR target/113871
	* config/i386/mmx.md (V248FI): Add V2BF mode.
	(V24FI_32): Ditto.

2024-02-27  Eric Botcazou  <ebotcazou@adacore.com>

	* tree-ssa-dse.cc (compute_trims): Fix description.  Return early
	if either ref->offset is not byte aligned or ref->size is not known
	to be equal to ref->max_size.
	(maybe_trim_complex_store): Fix description.
	(maybe_trim_constructor_store): Likewise.
	(maybe_trim_partially_dead_store): Likewise.

2024-02-27  Richard Earnshaw  <rearnsha@arm.com>

	* config/arm/mmintrin.h: Warn if this header is included without
	defining __ENABLE_DEPRECATED_IWMMXT.

2024-02-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114074
	* tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
	* tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
	Handle poly vs. non-poly multiplication correctly with respect
	to undefined behavior on overflow.

2024-02-27  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/114044
	* internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
	DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
	* internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
	expand_PARITY): Declare.
	* internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
	expand_CTZ, expand_FFS, expand_PARITY): New functions.
	(expand_POPCOUNT): Use expand_bitquery.

2024-02-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114081
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Perform manual dominator update for prologue peeling.
	(vect_do_peeling): Properly update dominators after adding the
	prologue-around guard.

2024-02-26  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
	(mstrict-X): Tag as "Optimization".

2024-02-26  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
	an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.

2024-02-26  Jakub Jelinek  <jakub@redhat.com>
	    H.J. Lu  <hjl.tools@gmail.com>

	PR rtl-optimization/113617
	* varasm.cc (default_elf_select_rtx_section): For
	references to private symbols in comdat sections
	use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
	or .rodata.<comdat> comdat sections.

2024-02-26  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114099
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Create and fill in a needed virtual LC PHI for the alternate
	exits.  Remove code dealing with that missing.

2024-02-26  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114068
	* tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
	New function.
	(slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
	on the main exit if needed.  Remove band-aid for the case
	it was missing.

2024-02-26  H.J. Lu  <hjl.tools@gmail.com>

	PR target/114097
	* config/i386/i386-options.cc (ix86_set_func_type): Check
	interrupt instead of noreturn attribute.

2024-02-26  Jakub Jelinek  <jakub@redhat.com>

	* config/i386/i386.cc (ix86_bitint_type_info): Add support for
	!TARGET_64BIT.

2024-02-26  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114090
	* match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
	Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
	types.
	((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.

2024-02-26  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114084
	* fold-const.cc (fold_binary_loc): Avoid the final associate_trees
	if all subtrees of var0 come from one of the op0 or op1 operands
	and all subtrees of con0 come from the other one.  Don't clear
	variables which are never used afterwards.

2024-02-26  Richard Biener  <rguenther@suse.de>

	PR middle-end/114070
	* genmatch.cc (parser::parse_c_expr): Do not record operand
	lists but only mark operators used.
	* match.pd ((c ? a : b) op (c ? d : e)  -->  c ? (a op d) : (b op e)):
	Properly guard the case of tcc_comparison changing the VEC_COND
	value operand type.

2024-02-26  Jakub Jelinek  <jakub@redhat.com>

	PR target/114094
	* config/i386/i386.cc (x86_function_profiler): Add missing new-line
	to printed instruction.

2024-02-26  H.J. Lu  <hjl.tools@gmail.com>

	PR target/114098
	* config/i386/amxtileintrin.h (_tile_loadconfig): Use
	__builtin_ia32_ldtilecfg.
	(_tile_storeconfig): Use __builtin_ia32_sttilecfg.
	* config/i386/i386-builtin.def (BDESC): Add
	__builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
	* config/i386/i386-expand.cc (ix86_expand_builtin): Handle
	IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
	* config/i386/i386.md (ldtilecfg): New pattern.
	(sttilecfg): Likewise.

2024-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	PR tree-optimization/113205
	* tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
	the proposed layout if it does not allow a source partition with
	layout 2 to keep that layout.

2024-02-24  Jakub Jelinek  <jakub@redhat.com>

	* builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
	* combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
	* double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
	* genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
	(mk_attr_alt): Use HOST_WIDE_INT_0 macro.
	* genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
	macros.
	* ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
	* loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
	* pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
	HOST_WIDE_INT_UC macros.
	* rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
	* tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
	* tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
	* tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
	macros.
	* wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
	* config/i386/constraints.md (define_constraint "L"): Use
	HOST_WIDE_INT_C macro.
	* config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
	macro.
	(movl + movb peephole2): Likewise.
	* config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
	(const_32bit_mask): Likewise.

2024-02-24  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/114073
	* gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
	VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
	types like vector or complex types.
	(gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
	types.  Fix up VIEW_CONVERT_EXPR handling.  Allow merging
	VIEW_CONVERT_EXPR from non-integral/pointer types with a store.

2024-02-23  Robin Dapp  <rdapp@ventanamicro.com>

	PR target/114028
	* config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
	Return false if inner mode is already Pmode.
	(rvv_builder::is_all_same_sequence): New function.
	(expand_vec_init): Emit broadcast if sequence is all same.

2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113613
	* config/aarch64/aarch64-early-ra.cc
	(early_ra::m_current_region): New member variable.
	(early_ra::m_fpr_recency): Likewise.
	(early_ra::start_new_region): Bump m_current_region.
	(early_ra::allocate_colors): Prefer less recently used registers
	in the event of a tie.  Add a comment to explain why we prefer(ed)
	higher-numbered registers.
	(early_ra::find_oldest_color): Prefer less recently used registers
	here too.
	(early_ra::finalize_allocation): Update recency information for
	allocated registers.
	(early_ra::process_blocks): Initialize m_current_region and
	m_fpr_recency.

2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113295
	* config/aarch64/aarch64-early-ra.cc
	(early_ra::test_strictness): New enum.
	(early_ra::is_chain_candidate): Add a strictness parameter to
	control whether only correctness matters, or whether both correctness
	and heuristics should be used.  Handle multiple levels of equivalence.
	(early_ra::find_related_start): Update call accordingly.
	(early_ra::strided_polarity_pref): Likewise.
	(early_ra::form_chains): Likewise.
	(early_ra::try_to_chain_allocnos): Use is_chain_candidate in
	correctness mode rather than trying to inline the test.

2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113295
	* config/aarch64/aarch64-early-ra.cc
	(early_ra::find_related_start): Account for definitions by shared
	registers when testing for a single register definition.
	(early_ra::accumulate_defs): New function.
	(early_ra::record_copy): If A shares B's register, fold A's
	definition information into B's.  Fold A's use information into B's.

2024-02-23  H.J. Lu  <hjl.tools@gmail.com>

	* configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
	if R_X86_64_CODE_6_GOTTPOFF is supported.
	* config.in: Regenerated.
	* configure: Likewise.
	* config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
	UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.

2024-02-23  Richard Earnshaw  <rearnsha@arm.com>

	PR target/108120
	* config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
	Gate with ARM_HAVE_NEON_<MODE>_ARITH.

2024-02-23  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/114054
	* expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
	temp variable instead of target parameter for result.

2024-02-23  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114040
	* gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
	Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
	probability from likely to unlikely.  When handling the true true
	store, first cast to limb_access_type and then to l's type.

2024-02-23  Richard Biener  <rguenther@suse.de>

	PR target/90785
	* config.gcc: Add ia64*-*-* to the list of obsoleted targets.

2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>

	PR other/109668
	* config/riscv/arch-canonicalize: Move to python3
	* config/riscv/multilib-generator: Likewise

2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>

	* doc/invoke.texi: Document -mcpu.

2024-02-23  Lulu Cheng  <chenglulu@loongson.cn>

	* configure: Regenerate.
	* configure.ac: Add parameter "--fatal-warnings" to assemble
	when checking whether the assemble support conditional branch
	relaxation.

2024-02-22  Jakub Jelinek  <jakub@redhat.com>

	PR c/114007
	* doc/extend.texi: (__extension__): Remove comments about scope
	tokens vs. two colons.

2024-02-22  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/109804
	* gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
	DEMANGLE_COMPONENT_UNNAMED_TYPE.

2024-02-22  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114048
	* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
	can also produce -1 off.

2024-02-22  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/114027
	* tree-vect-loop.cc (vecctorizable_reduction): Use optimized
	condition reduction classification only for single-element
	chains.

2024-02-22  Jakub Jelinek  <jakub@redhat.com>

	PR ipa/111960
	* profile-count.h (profile_count::dump): Remove overload with
	char * first argument.
	* profile-count.cc (profile_count::dump): Change overload with char *
	first argument which uses sprintf into the overfload with FILE *
	first argument and use fprintf instead.  Remove overload which wrapped
	it.

2024-02-22  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113993
	* tree-call-cdce.cc (get_no_error_domain): Handle
	BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}.  Handle
	BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
	REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
	the as the F128 suffixed cases, otherwise as non-suffixed ones.
	Handle BUILT_IN_{EXP,POW}10L for
	REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
	as (-inf, 4932).

2024-02-22  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/114038
	* gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
	loop exit condition if end is divisible by limb_prec.

2024-02-22  YunQiang Su  <syq@gcc.gnu.org>

	* doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
	problem of mabi=, mno-flush-func, mexplicit-relocs;
	add missing leading - of mbranch-cost option.
	* config/mips/mips.opt.urls: Regenerate.

2024-02-22  Kewen Lin  <linkw@linux.ibm.com>

	PR target/109987
	* config/rs6000/constraints.md (we): Update internal doc without
	referring to option -mpower9-vector.
	* config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
	special handlings.
	* config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
	OTHER_P8_VECTOR_MASKS): Merge to ...
	(OTHER_VSX_VECTOR_MASKS): ... here.
	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
	some error message handlings and explicit option mask adjustments on
	explicit option power{8,9}-vector conflicting with other options.
	(rs6000_print_isa_options): Update comments.
	(rs6000_disable_incompatible_switches): Remove power{8,9}-vector
	related array items and handlings.
	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
	special handlings.
	* config/rs6000/rs6000.opt: Make option power{8,9}-vector as
	WarnRemoved.
	* doc/extend.texi: Remove documentation referring to option
	-mpower8-vector.
	* doc/invoke.texi: Remove documentation for option
	-mpower{8,9}-vector and adjust some documentation referring to them.
	* doc/md.texi: Update documentation for constraint we.
	* doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.

2024-02-22  Pan Li  <pan2.li@intel.com>

	PR target/114017
	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
	the version to 0.12.

2024-02-21  Edwin Lu  <ewlu@rivosinc.com>

	* config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert

2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
	    Robin Dapp  <rdapp.gcc@gmail.com>

	* config/riscv/generic-ooo.md (generic_ooo): Move reservation
	(generic_ooo_vec_load): Ditto
	(generic_ooo_vec_store): Ditto
	(generic_ooo_vec_loadstore_seg): Ditto
	(generic_ooo_vec_alu): Ditto
	(generic_ooo_vec_fcmp): Ditto
	(generic_ooo_vec_imul): Ditto
	(generic_ooo_vec_fadd): Ditto
	(generic_ooo_vec_fmul): Ditto
	(generic_ooo_crypto): Ditto
	(generic_ooo_perm): Ditto
	(generic_ooo_vec_reduction): Ditto
	(generic_ooo_vec_ordered_reduction): Ditto
	(generic_ooo_vec_idiv): Ditto
	(generic_ooo_vec_float_divsqrt): Ditto
	(generic_ooo_vec_mask): Ditto
	(generic_ooo_vec_vesetvl): Ditto
	(generic_ooo_vec_setrm): Ditto
	(generic_ooo_vec_readlen): Ditto
	* config/riscv/riscv.md: Include generic-vector-ooo
	* config/riscv/generic-vector-ooo.md: New file. To here

2024-02-21  Edwin Lu  <ewlu@rivosinc.com>

	* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
	(generic_ooo_branch): Ditto
	* config/riscv/generic.md (generic_sfb_alu): Ditto
	(generic_fmul_half): Ditto
	* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
	* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
	(sifive_7_popcount): Ditto
	* config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
	* config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
	* config/riscv/vector.md: Change rdfrm to fmove
	* config/riscv/zc.md: Change pushpop to load/store

2024-02-21  Jonathan Wakely  <jwakely@redhat.com>

	* doc/invoke.texi (Warning Options): Fix typos.

2024-02-21  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
	* config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
	* config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.

2024-02-21  Martin Jambor  <mjambor@suse.cz>

	PR ipa/113476
	* ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
	initializers in the contructor.
	(ipa_node_params::~ipa_node_params): Release lattices as a vector.
	* ipa-cp.h: New file.
	* ipa-cp.cc: Include sreal.h and ipa-cp.h.
	(ipcp_value_source): Move to ipa-cp.h.
	(ipcp_value_base): Likewise.
	(ipcp_value): Likewise.
	(ipcp_lattice): Likewise.
	(ipcp_agg_lattice): Likewise.
	(ipcp_bits_lattice): Likewise.
	(ipcp_vr_lattice): Likewise.
	(ipcp_param_lattices): Likewise.
	(ipa_get_parm_lattices): Remove assert latticess is non-NULL.
	(ipa_value_from_jfunc): Adjust a check for empty lattices.
	(ipa_context_from_jfunc): Likewise.
	(ipa_agg_value_from_jfunc): Likewise.
	(merge_agg_lats_step): Do not memset new aggregate lattices to zero.
	(ipcp_propagate_stage): Allocate lattices in a vector as opposed to
	just in contiguous memory.
	(ipcp_store_vr_results): Adjust a check for empty lattices.
	* auto-profile.cc: Include sreal.h and ipa-cp.h.
	* cgraph.cc: Likewise.
	* cgraphclones.cc: Likewise.
	* cgraphunit.cc: Likewise.
	* config/aarch64/aarch64.cc: Likewise.
	* config/i386/i386-builtins.cc: Likewise.
	* config/i386/i386-expand.cc: Likewise.
	* config/i386/i386-features.cc: Likewise.
	* config/i386/i386-options.cc: Likewise.
	* config/i386/i386.cc: Likewise.
	* config/rs6000/rs6000.cc: Likewise.
	* config/s390/s390.cc: Likewise.
	* gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
	files to be included in gtype-desc.cc.
	* gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
	* ipa-devirt.cc: Likewise.
	* ipa-fnsummary.cc: Likewise.
	* ipa-icf.cc: Likewise.
	* ipa-inline-analysis.cc: Likewise.
	* ipa-inline-transform.cc: Likewise.
	* ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
	* ipa-modref.cc: Include sreal.h and ipa-cp.h.
	* ipa-param-manipulation.cc: Likewise.
	* ipa-predicate.cc: Likewise.
	* ipa-profile.cc: Likewise.
	* ipa-prop.cc: Likewise.
	(ipa_node_params_t::duplicate): Assert new lattices remain empty
	instead of setting them to NULL.
	* ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
	* ipa-split.cc: Likewise.
	* ipa-sra.cc: Likewise.
	* ipa-strub.cc: Likewise.
	* ipa-utils.cc: Likewise.
	* ipa.cc: Likewise.
	* toplev.cc: Likewise.
	* tree-ssa-ccp.cc: Likewise.
	* tree-ssa-sccvn.cc: Likewise.
	* tree-vrp.cc: Likewise.

2024-02-21  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
	Armv8.7-a.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
	Use aarch64_gen_compare_zero_and_branch rather than emitting
	a CBZ directly.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
	Remove duplicated call.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
	Check that each individual piece of state is shared in the same
	way, rather than using an aggregate check for PSTATE.ZA.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
	In the code that commits a lazy save, only zero ZA if the function
	has ZA state.  Similarly zero ZT0 if the function has ZT0 state.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
	directly inserting the associated sequence
	* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
	...here instead.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113995
	* config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
	fold the SVE allocation into the initial allocation if the
	initial allocation includes a VG save.

2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113220
	* cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
	contain jumps even if called after initial RTL expansion.
	* mode-switching.cc: Include cfgbuild.h.
	(optimize_mode_switching): Allow the sequence returned by the
	emit hook to contain internal jumps.  Record which blocks
	contain such jumps and split the blocks at the end.
	* config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
	non-debug insns when scanning the sequence.

2024-02-21  Tobias Burnus  <tburnus@baylibre.com>

	* config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
	* config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.

2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>

	* doc/invoke.texi (-mmcu): Add information about MCU specs.

2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>

	* doc/invoke.texi (-minrt): Clarify that main
	must take no arguments.

2024-02-20  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/builtins.def: Use function prototypes of given size
	and signedness.
	* config/avr/avr.cc (avr_init_builtins): Adjust types required
	by builtins.def.
	* doc/extend.texi (AVR Built-in Functions): Adjust accordingly.

2024-02-20  Georg-Johann Lay  <avr@gjlay.de>

	* doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
	instead of @table.

2024-02-20  Will Hawkins  <hawkinsw@obs.cr>

	* config/bpf/bpf.opt: Add help information for -mcpu.

2024-02-20  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113805
	* config/aarch64/aarch64-passes.def (pass_late_track_speculation):
	New pass.
	* config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
	Declare.
	* config/aarch64/aarch64.md (is_call): New attribute.
	(*and<mode>3nr_compare0): Rename to...
	(@aarch64_and<mode>3nr_compare0): ...this.
	* config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
	(aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
	* config/aarch64/aarch64-speculation.cc: Update file comment to
	describe the new late pass.
	(aarch64_do_track_speculation): Handle is_call insns like other calls.
	(pass_track_speculation): Add an is_late member variable.
	(pass_track_speculation::gate): Run the late pass for streaming-
	compatible functions and the early pass for other functions.
	(make_pass_track_speculation): Update accordingly.
	(make_pass_late_track_speculation): New function.
	* config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
	function.
	(aarch64_guard_switch_pstate_sm): Use it.

2024-02-19  Iain Sandoe  <iain@sandoe.co.uk>

	* config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
	Register these builtins with a pointer to uint64_t rather than unsigned
	DI mode.

2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>

	PR target/113615
	* config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
	Conditionalize on '!TARGET_RDNA2_PLUS'.
	* config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
	(gcn_expand_reduc_scalar):
	'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.

2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
	'__gfx90a__' target CPU definition.  Add some safeguards for the future.

2024-02-19  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/54052
	* rtl-ssa/blocks.cc (function_info::place_phis): Filter
	local defs by LR_OUT.

2024-02-19  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113967
	* match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
	in condition that @rpos is multiple of vector element size.

2024-02-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113696
	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
	Suppress vsetvl fusion.

2024-02-18  H.J. Lu  <hjl.tools@gmail.com>

	PR target/113912
	* config/i386/i386.cc (ix86_can_use_push2pop2): New.
	(ix86_pro_and_epilogue_can_use_push2pop2): Use it.
	(ix86_emit_save_regs): Don't generate push2 if
	ix86_can_use_push2pop2 return false.
	(ix86_expand_epilogue): Don't generate pop2 if
	ix86_can_use_push2pop2 return false.

2024-02-18  Georg-Johann Lay  <avr@gjlay.de>

	* doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
	Note on complete device support.

2024-02-18  Georg-Johann Lay  <avr@gjlay.de>

	* doc/extend.texi (AVR Function Attributes): Fuse description
	of "signal" and "interrupt" attribute.  Link pseudo instruction.

2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
	symbol type conversions.
	(__cacop_d): Likewise.
	(__cpucfg): Likewise.
	(__asrtle_d): Likewise.
	(__asrtgt_d): Likewise.
	(__lddir_d): Likewise.
	(__ldpte_d): Likewise.
	(__crc_w_b_w): Likewise.
	(__crc_w_h_w): Likewise.
	(__crc_w_w_w): Likewise.
	(__crc_w_d_w): Likewise.
	(__crcc_w_b_w): Likewise.
	(__crcc_w_h_w): Likewise.
	(__crcc_w_w_w): Likewise.
	(__crcc_w_d_w): Likewise.
	(__csrrd_w): Likewise.
	(__csrwr_w): Likewise.
	(__csrxchg_w): Likewise.
	(__csrrd_d): Likewise.
	(__csrwr_d): Likewise.
	(__csrxchg_d): Likewise.
	(__iocsrrd_b): Likewise.
	(__iocsrrd_h): Likewise.
	(__iocsrrd_w): Likewise.
	(__iocsrrd_d): Likewise.
	(__iocsrwr_b): Likewise.
	(__iocsrwr_h): Likewise.
	(__iocsrwr_w): Likewise.
	(__iocsrwr_d): Likewise.
	(__frecipe_s): Likewise.
	(__frecipe_d): Likewise.
	(__frsqrte_s): Likewise.
	(__frsqrte_d): Likewise.

2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
	function return value type to unsigned short.

2024-02-16  Edwin Lu  <ewlu@rivosinc.com>

	* doc/sourcebuild.texi: add scan-assembler-bound

2024-02-16  Jason Merrill  <jason@redhat.com>

	* gdbhooks.py: Fix regex syntax.

2024-02-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113895
	* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
	consistency checking when there are out-of-bound array
	accesses.  Allow -1 off when from an array reference with
	constant index.

2024-02-16  Kito Cheng  <kito.cheng@sifive.com>

	PR target/106543
	* config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
	pattern.

2024-02-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	* doc/sourcebuild.texi (Effective-Target Keywords, Other
	attribugs): Document linker_plugin.
	(Require Support): Document dg-require-linker-plugin.

2024-02-16  Kito Cheng  <kito.cheng@sifive.com>

	PR target/109349
	* common/config/riscv/riscv-common.cc (riscv_arch_help): New.
	* config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
	(RISCV_MINOR_VERSION_BASE): Ditto.
	(RISCV_REVISION_VERSION_BASE): Ditto.
	* config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
	rather than magic number.
	* config/riscv/riscv.h (riscv_arch_help): New.
	(EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
	(DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
	--print-supported-extensions.
	* config/riscv/riscv.opt (march=help): New.
	(print-supported-extensions): New.
	(-print-supported-extensions): New.
	* doc/invoke.texi (RISC-V Options): Document -march=help.

2024-02-16  Tejas Belagod  <tejas.belagod@arm.com>

	PR target/113780
	* config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
	for indirect calls with 4 or more arguments in pac-enabled functions.

2024-02-15  David Faust  <david.faust@oracle.com>

	* config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
	use ldxb instead of ldxh.

2024-02-15  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113921
	* cfgrtl.h (prepend_insn_to_edge): New declaration.
	* cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
	comment.
	(prepend_insn_to_edge): New function.
	* cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
	insert_insn_on_edge.

2024-02-15  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/111156
	* tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
	at the pattern stmt if any.

2024-02-15  Georg-Johann Lay  <avr@gjlay.de>

	PR target/113927
	* config/avr/avr.h (AVR_HAVE_ADIW): New macro.
	* config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
	* config/avr/avr.cc (avr_adiw_reg_p): New function.
	(avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
	Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
	* config/avr/avr.md: Same.
	(attr "isa") <tiny, no_tiny>: Remove.
	<adiw, no_adiw>: Add.
	(define_insn, define_insn_and_split): When an alternative has
	constraint "w", then set attribute "isa" to "adiw".
	* config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
	Built-in define __AVR_HAVE_ADIW__.
	* doc/invoke.texi (AVR Options): Document it.

2024-02-15  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn-valu.md
	(vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
	* config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
	details are supported on RDNA devices.

2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/113508
	* doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
	usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
	smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
	Add sentence about what the mode m is.

2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>

	* doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
	smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
	var.

2024-02-15  Richard Biener  <rguenther@suse.de>

	* tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
	stmts.

2024-02-15  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113567
	* gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
	_BitInt multiplication, division or modulo with
	SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
	force the affected inputs into a new SSA_NAME.

2024-02-14  Uros Bizjak  <ubizjak@gmail.com>

	PR target/113871
	* config/i386/mmx.md (V248FI): New mode iterator.
	(V24FI_32): DItto.
	(vec_shl_<V248FI:mode>): New expander.
	(vec_shl_<V24FI_32:mode>): Ditto.
	(vec_shr_<V248FI:mode>): Ditto.
	(vec_shr_<V24FI_32:mode>): Ditto.
	* config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
	(vec_shr_<V248FI:mode>): Ditto.

2024-02-14  Jan Hubicka  <jh@suse.cz>

	PR tree-optimization/111054
	* tree-ssa-loop-split.cc (split_loop): Check for profile being present.

2024-02-14  Tamar Christina  <tamar.christina@arm.com>

	* tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.

2024-02-14  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113910
	* bitmap.cc (bitmap_hash): Mix the full element "hash" to
	the hashval_t hash.

2024-02-14  Jakub Jelinek  <jakub@redhat.com>

	* pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
	(pp_integer_with_precision): For unsigned ptrdiff_t printing
	with u, o or x print ptrdiff_t argument converted to
	unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.

2024-02-14  Richard Biener  <rguenther@suse.de>

	PR middle-end/113576
	* expr.cc (do_store_flag): For vector bool compares of vectors
	with padding zero that.
	* dojump.cc (do_compare_and_jump): Likewise.

2024-02-14  Gerald Pfeifer  <gerald@pfeifer.com>

	* doc/install.texi (Prerequisites): Update gettext link.

2024-02-13  H.J. Lu  <hjl.tools@gmail.com>

	PR target/113876
	* config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
	Return false if the incoming stack isn't 16-byte aligned.

2024-02-13  Tobias Burnus  <tburnus@baylibre.com>

	PR middle-end/113904
	* omp-general.cc (struct omp_ts_info): Update for splitting of
	OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
	* omp-selectors.h (enum omp_tp_type): Replace
	OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.

2024-02-13  Monk Chiang  <monk.chiang@sifive.com>

	PR target/113742
	* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
	recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.

2024-02-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113895
	* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
	offset to discover constant array indices in bits, handle
	COMPONENT_REF to bitfields.

2024-02-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113831
	* tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
	typo in comment.

2024-02-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113902
	* tree-vect-loop.cc (move_early_exit_stmts): Track
	last_seen_vuse for VUSE updating.

2024-02-13  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113734
	* tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
	an early break loop as partial.

2024-02-13  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113898
	* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
	missing accumulated off adjustment.

2024-02-13  Jakub Jelinek  <jakub@redhat.com>

	* hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
	instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
	it against UINT_MAX and ULONG_MAX.

2024-02-13  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic-core.h (emit_diagnostic_valist): Rename overload
	to...
	(emit_diagnostic_valist_meta): ...this.
	* diagnostic.cc (emit_diagnostic_valist): Likewise, to...
	(emit_diagnostic_valist_meta): ...this.

2024-02-12  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113849
	* gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
	fast path for widening casts where !m_upwards_2limb and lhs_type
	has precision which is a multiple of limb_prec.

2024-02-12  Jakub Jelinek  <jakub@redhat.com>

	PR c++/113674
	* attribs.cc (extract_attribute_substring): Remove.
	(lookup_scoped_attribute_spec): Don't call it.

2024-02-12  Jakub Jelinek  <jakub@redhat.com>

	* gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
	and cast to fmt_size_t instead of %lu and cast to unsigned long.

2024-02-12  Christophe Lyon  <christophe.lyon@linaro.org>

	* Makefile.in: Add no-info dependency.
	* configure.ac: Set BUILD_INFO=no-info if makeinfo is not
	available.
	* configure: Regenerate.

2024-02-12  Iain Sandoe  <iain@sandoe.co.uk>

	PR target/113855
	* config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
	available to all sub-targets.
	* config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
	* config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.

2024-02-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113831
	PR tree-optimization/108355
	* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
	we see variable array indices and get_ref_base_and_extent
	can resolve those to constants fix up the ops to constants
	as well.
	(ao_ref_init_from_vn_reference): Use 'off' member for
	ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
	(valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.

2024-02-12  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
	Replace args to arguments for misspelled term.

2024-02-12  Georg-Johann Lay  <avr@gjlay.de>

	PR target/112944
	* config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
	<*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
	when not linked with -mrodata-in-ram.

2024-02-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113863
	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
	Record crossed virtual PHIs.
	* tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
	virtual PHIs.

2024-02-10  Marek Polacek  <polacek@redhat.com>

	DR 2237
	PR c++/107126
	PR c++/97202
	* doc/invoke.texi: Document -Wtemplate-id-cdtor.

2024-02-10  Jakub Jelinek  <jakub@redhat.com>

	* gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
	computation of idx for i == 4 of bitint_prec_huge.

2024-02-10  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/110754
	* gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
	decls create PARM_DECL with pointer to original type, set
	TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
	DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
	(adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
	wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
	(lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
	of the var as argument.

2024-02-10  Jakub Jelinek  <jakub@redhat.com>

	* pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
	size_t and precision 4 for ptrdiff_t.  Formatting fix.
	(pp_format): Document %{t,z}{d,i,u,o,x}.  Implement t and z modifiers.
	Formatting fixes.
	(test_pp_format): Test t and z modifiers.
	* gcc.cc (read_specs): Use %td instead of %ld and casts to long.

2024-02-10  Jakub Jelinek  <jakub@redhat.com>

	* ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
	sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
	and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
	* tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
	and casts to fmt_size_t instead of "%ld" and casts to long.
	(print_value_expr_statistics, print_type_hash_statistics): Likewise.
	* dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
	instead of "%lu" and casts to unsigned long.
	* gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
	unsigned long.
	* tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
	and casts to fmt_size_t instead of "%ld" and casts to long.
	* cfgexpand.cc (dump_stack_var_partition): Use
	HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
	and casts to unsigned long.
	* gengtype.cc (adjust_field_rtx_def): Likewise.
	* tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
	and casts to fmt_size_t instead of "%ld" and casts to long.
	* postreload-gcse.cc (dump_hash_table): Likewise.
	* ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
	and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
	(ggc_internal_alloc, ggc_free): Likewise.
	* genpreds.cc (write_lookup_constraint_1): Likewise.
	(write_insn_constraint_len): Likewise.
	* tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
	and casts to fmt_size_t instead of "%ld" and casts to long.
	* varasm.cc (output_constant_pool_contents): Use
	HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
	* var-tracking.cc (dump_var): Likewise.

2024-02-09  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113783
	* gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
	through VIEW_CONVERT_EXPR for final cast checks.  Handle
	VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
	INTEGER_TYPEs.
	(gimple_lower_bitint): Don't merge mergeable operations or other
	casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
	* expr.cc (expand_expr_real_1): Don't use convert_modes if either
	mode is BLKmode.

2024-02-09  Jakub Jelinek  <jakub@redhat.com>

	* hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
	HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
	HOST_SIZE_T_PRINT_HEX_PURE): Define.
	* ira-conflicts.cc (build_conflict_bit_table): Use it.  Formatting
	fixes.

2024-02-09  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113415
	* cfgexpand.cc (expand_asm_stmt): For asm goto, use
	duplicate_insn_chain to duplicate after_rtl_seq sequence instead
	of hand written loop with emit_insn of copy_insn and emit original
	after_rtl_seq on the last edge.

2024-02-09  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113818
	* gimple-lower-bitint.cc (add_eh_edge): New function.
	(bitint_large_huge::handle_load,
	bitint_large_huge::lower_mergeable_stmt,
	bitint_large_huge::lower_muldiv_stmt): Use it.

2024-02-09  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113774
	* gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
	emit any comparison if m_first and low + 1 is equal to
	m_upwards_2limb, simplify condition for that.  If not
	single_comparison, not m_first and we can prove that the idx <= low
	comparison will be always true, emit instead of idx <= low
	comparison low <= low such that cfg cleanup will optimize it at
	the end of the pass.

2024-02-08  Aldy Hernandez  <aldyh@redhat.com>

	PR tree-optimization/113735
	* value-relation.cc (equiv_oracle::add_equiv_to_block): Call
	limit_check().

2024-02-08  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
	(main, print_mcu, diagnose_mrodata_in_ram): Pass it down.

2024-02-08  H.J. Lu  <hjl.tools@gmail.com>

	PR target/113711
	PR target/113733
	* config/i386/constraints.md: List all constraints with j prefix.
	(j>): Change auto-dec to auto-inc in documentation.
	(je): Changed to a memory constraint with APX NDD TLS operand
	check.
	(jM): New memory constraint for APX NDD instructions.
	(jO): Likewise.
	* config/i386/i386-protos.h (x86_poff_operand_p): Removed.
	* config/i386/i386.cc (x86_poff_operand_p): Likewise.
	* config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
	(*add<mode>_1[SWI48]): Use je and jM.
	(addsi_1_zext): Use jM.
	(*addv<dwi>4_doubleword_1[DWI]): Likewise.
	(*sub<mode>_1[SWI]): Use jM.
	(@add<mode>3_cc_overflow_1[SWI]): Likewise.
	(*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
	(*and<dwi>3_doubleword): Likewise.
	(*anddi_1): Use jM.
	(*andsi_1_zext): Likewise.
	(*and<mode>_1[SWI24]): Likewise.
	(*<code><dwi>3_doubleword[any_or]): Use rjO
	(*code<mode>_1[any_or SWI248]): Use jM.
	(*<code>si_1_zext[zero_extend + any_or]): Likewise.
	* config/i386/predicates.md (apx_ndd_memory_operand): New.
	(apx_ndd_add_memory_operand): Likewise.

2024-02-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/113824
	* config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
	* doc/avr-mmcu.texi: Rebuild.

2024-02-08  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113808
	* tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
	value cross iterations.

2024-02-08  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
	defines __AVR_PM_BASE_ADDRESS__ if the core has it.

2024-02-08  Richard Biener  <rguenther@suse.de>

	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
	Revert last change to dr_may_alias_p.

2024-02-08  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
	cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
	Remove spec asm_misc.
	* config/avr/specs.h: Same.

2024-02-08  Pan Li  <pan2.li@intel.com>

	PR target/113766
	* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
	sure the c.arg_num is >= 2 before checking.
	(struct build_frm_base): Ditto.
	(struct narrow_alu_def): Ditto.

2024-02-07  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113796
	* tree-if-conv.cc (combine_blocks): Wipe range-info before
	replacing PHIs and inserting predicates.

2024-02-07  Roger Sayle  <roger@nextmovesoftware.com>
	    Uros Bizjak  <ubizjak@gmail.com>

	PR target/113690
	* config/i386/i386-features.cc (timode_convert_cst): New helper
	function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
	CONST_VECTOR.
	(timode_scalar_chain::convert_op): Use timode_convert_cst.
	(timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
	Use timode_convert_cst.

2024-02-07  Victor Do Nascimento  <victor.donascimento@arm.com>

	* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
	* config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
	(AARCH64_FL_DEBUGv8p9): Likewise.
	(AARCH64_FL_FGT2): Likewise.Likewise.
	(AARCH64_FL_ITE): Likewise.
	(AARCH64_FL_PFAR): Likewise.
	(AARCH64_FL_PMUv3_ICNTR): Likewise.
	(AARCH64_FL_PMUv3_SS): Likewise.
	(AARCH64_FL_PMUv3p9): Likewise.
	(AARCH64_FL_RASv2): Likewise.
	(AARCH64_FL_S1PIE): Likewise.
	(AARCH64_FL_S1POE): Likewise.
	(AARCH64_FL_S2PIE): Likewise.
	(AARCH64_FL_S2POE): Likewise.
	(AARCH64_FL_SCTLR2): Likewise.
	(AARCH64_FL_SEBEP): Likewise.
	(AARCH64_FL_SPE_FDS): Likewise.
	(AARCH64_FL_TCR2): Likewise.

2024-02-07  Richard Biener  <rguenther@suse.de>

	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
	Only check whether reads are in-bound in places that are not safe.
	Fix dependence check.  Add missing newline.  Clarify comments.

2024-02-07  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113750
	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
	for single predecessor when doing early break vect.
	* tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
	after labels.

2024-02-07  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113731
	* gimple-iterator.cc (gsi_move_before): Take new parameter for update
	method.
	* gimple-iterator.h (gsi_move_before): Default new param to
	GSI_SAME_STMT.
	* tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
	GSI_NEW_STMT.

2024-02-07  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113756
	* range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
	use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
	of lh_bits value and mask.

2024-02-07  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113753
	* wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
	UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
	not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
	so that they start with r[half_blocks_needed] lowest bit.  Fix up
	computation of top mask for SIGNED.

2024-02-07  Pan Li  <pan2.li@intel.com>

	PR target/113766
	* config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
	the signature of func.
	* config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
	* config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
	overloaded func with empty args error.

2024-02-06  H.J. Lu  <hjl.tools@gmail.com>

	PR target/113689
	* config/i386/i386.cc (x86_64_select_profile_regnum): Return
	R10_REG after sorry.

2024-02-06  Andrew Carlotti  <andrew.carlotti@arm.com>

	* config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
	Move before new caller, and add ".default" suffix.
	(get_suffixed_assembler_name): New.
	(make_resolver_func): Use get_suffixed_assembler_name.
	(aarch64_generate_version_dispatcher_body): Redo name mangling.

2024-02-06  Jakub Jelinek  <jakub@redhat.com>

	PR target/113763
	* config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
	element from std::pair<unsigned int, char> to an unnamed struct.
	Adjust uses of tile range variable.

2024-02-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
	(pre_vsetvl::remove_vsetvl_pre_insns): Ditto.

2024-02-06  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/110676
	* gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
	reset maxlen to sizetype maximum.

2024-02-06  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113736
	* gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
	var's address space for MEM_REF or VIEW_CONVERT_EXPRs.

2024-02-06  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113759
	* tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
	or from_unsignedN differs from properties of typeN, update typeN
	to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
	uselessly convertible to typeN, convert it using fold_convert or
	build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
	(convert_plusminus_to_widen): Likewise.

2024-02-06  Tejas Belagod  <tejas.belagod@arm.com>

	PR target/112577
	* config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
	vector structure modes correctly.

2024-02-05  Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/thead.cc (th_print_operand_address): Fix compiler
	warning.

2024-02-05  H.J. Lu  <hjl.tools@gmail.com>

	PR target/113689
	* config/i386/i386.cc (x86_64_select_profile_regnum): New.
	(x86_function_profiler): Call x86_64_select_profile_regnum to
	get a scratch register for large model profiling.

2024-02-05  Richard Ball  <richard.ball@arm.com>

	* config/arm/arm.cc (arm_output_mi_thunk): Emit
	insn for bti_c when bti is enabled.

2024-02-05  Xi Ruoyao  <xry111@xry111.site>

	* config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
	neg.

2024-02-05  Xi Ruoyao  <xry111@xry111.site>

	* config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
	(neg<mode>2): Change the mode iterator from MSA to IMSA because
	in FP arithmetic we cannot use (0 - x) for -x.
	(neg<mode>2): New define_insn to implement FP vector negation,
	using a bnegi instruction to negate the sign bit.

2024-02-05  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113707
	* tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
	checking the avail set treat out-of-region defines as
	available.

2024-02-05  Richard Biener  <rguenther@suse.de>

	* tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
	the default mode when building a pointer.

2024-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113737
	* gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
	has just a single label, remove it and make single successor edge
	EDGE_FALLTHRU.

2024-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR target/113059
	* config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
	Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
	df_analyze call.

2024-02-05  Richard Biener  <rguenther@suse.de>

	PR target/113255
	* config/i386/i386-expand.cc
	(expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
	Use a new pseudo for the skipped number of bytes.

2024-02-05  Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
	* doc/invoke.texi (RISC-V Options): Add sifive-p450,
	sifive-p670.

2024-02-05  Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.md: Include sifive-p400.md.
	* config/riscv/sifive-p400.md: New file.
	* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
	Add sifive_p400.
	* config/riscv/riscv.cc (sifive_p400_tune_info): New.
	* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
	* doc/invoke.texi (RISC-V Options): Add sifive-p400-series

2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

	* config/xtensa/xtensa.md (*eqne_zero_masked_bits):
	Add missing ":SI" to the match_operator.

2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

	* config/xtensa/xtensa.md (SHI): New mode iterator.
	(2 split patterns related to constsynth):
	Change to also accept HImode operands.

2024-02-04  Jeff Law  <jlaw@ventanamicro.com>

	* config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
	similarly.

2024-02-04  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
	incorrect expand.
	* config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
	(elmsgnbit): Likewise.
	(neg<mode:FVEC>2): New define_insn.
	* config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
	are now instantiated in simd.md.

2024-02-04  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
	use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
	MAX_MACHINE_MODE.

2024-02-04  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
	(loongarch_expand_vselect_vconcat): Ditto.
	(loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
	all 128-bit constant permutation situations.
	(loongarch_expand_lsx_shuffle): Adjust and rename function name.
	(loongarch_is_imm_set_shuffle): Renamed function name.
	(loongarch_expand_vec_perm_even_odd): Function forward declaration.
	(loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
	extract-even and extract-odd permutations.
	(loongarch_is_odd_extraction): Delete.
	(loongarch_is_even_extraction): Ditto.
	(loongarch_expand_vec_perm_const): Adjust.

2024-02-03  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113722
	* wide-int.cc (wi::bswap_large): Rename third argument from
	len to xlen and adjust use in safe_uhwi.  Add len variable, set
	it to BLOCKS_NEEDED (precision) and use it for clearing of val
	and as canonize argument.  Clear val using memset instead of
	a loop.

2024-02-03  Jakub Jelinek  <jakub@redhat.com>

	* ggc-common.cc (gt_pch_save): Allow addr to be equal to
	mmi.preferred_base + mmi.size - sizeof (void *).

2024-02-03  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
	* config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
	the ODR-violating locale declaration.

2024-02-02  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113588
	PR tree-optimization/113467
	* tree-vect-data-refs.cc
	(vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
	(vect_analyze_early_break_dependences): Update comments.

2024-02-02  John David Anglin  <danglin@gcc.gnu.org>

	PR target/59778
	* config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
	and PA_BUILTIN_SET_FPSR builtins.
	* (pa_builtins_icode): Declare.
	* (def_builtin, pa_fpu_init_builtins): New.
	* (pa_init_builtins): Initialize FPU builtins.
	* (pa_builtin_decl, pa_expand_builtin_1): New.
	* (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
	PA_BUILTIN_SET_FPSR builtins.
	* (pa_atomic_assign_expand_fenv): New.
	* config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
	UNSPECV constants.
	(get_fpsr, put_fpsr): New expanders.
	(get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
	insn patterns.

2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113697
	* config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.

2024-02-02  Jonathan Wakely  <jwakely@redhat.com>

	* doc/extend.texi (Common Type Attributes): Fix typo in
	description of hardbool.

2024-02-02  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113692
	* gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
	from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
	final_cast_p.

2024-02-02  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113699
	* gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
	uninitialized large/huge _BitInt SSA_NAME inputs.

2024-02-02  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113705
	* tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
	around wi::to_wide in order to compare value in prec precision.

2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>

	Revert:
	2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.

2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.

2024-02-02  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
	(riscv_pass_by_reference): Ditto.
	(riscv_fntype_abi): Ditto.

2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
	(pre_vsetvl::cleaup): Remove vsetvl_pre.
	(pre_vsetvl::remove_vsetvl_pre_insns): New function.

2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/larchintrin.h
	(__frecipe_s): Update function return type.
	(__frecipe_d): Ditto.
	(__frsqrte_s): Ditto.
	(__frsqrte_d): Ditto.

2024-02-02  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
	(loongarch_vector_costs::add_stmt_cost): Adjust.

2024-02-02  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md (unspec): Add
	UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
	(la_pcrel64_two_parts): New define_insn.
	* config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
	typo in the comment.
	(loongarch_call_tls_get_addr): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
	addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
	note to allow CSE addressing __tls_get_addr.
	(loongarch_legitimize_tls_address): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, address TLS IE symbols with
	la_pcrel64_two_parts.
	(loongarch_split_symbol): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, address symbols with
	la_pcrel64_two_parts.
	(loongarch_output_mi_thunk): Clean up unreachable code.  If
	-mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
	thunks with la_pcrel64_two_parts.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
	Add support for call36.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
	When the code model of the symbol is extreme and -mexplicit-relocs=auto,
	the macro instruction loading symbol address is not applicable.
	(loongarch_call_tls_get_addr): Adjust code.
	(loongarch_legitimize_tls_address): Likewise.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
	Add function declaration.
	* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
	For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
	is not allowed
	(loongarch_load_tls): Added macro support in extreme mode.
	(loongarch_call_tls_get_addr): Likewise.
	(loongarch_legitimize_tls_address): Likewise.
	(loongarch_force_address): Likewise.
	(loongarch_legitimize_move): Likewise.
	(loongarch_output_mi_thunk): Likewise.
	(loongarch_option_override_internal): Remove the code that detects
	explicit relocs status.
	(loongarch_handle_model_attribute): Likewise.
	* config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
	* config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
	(symbolic_off64_or_reg_operand): Likewise.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_load_tls):
	Load all types of tls symbols through one function.
	(loongarch_got_load_tls_gd): Delete.
	(loongarch_got_load_tls_ld): Delete.
	(loongarch_got_load_tls_ie): Delete.
	(loongarch_got_load_tls_le): Delete.
	(loongarch_call_tls_get_addr): Modify the called function name.
	(loongarch_legitimize_tls_address): Likewise.
	* config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
	(@load_tls<mode>): New template.
	(@got_load_tls_ld<mode>): Delete.
	(@got_load_tls_le<mode>): Delete.
	(@got_load_tls_ie<mode>): Delete.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
	(loongarch_legitimize_address): Add logical transformation code.

2024-02-01  Marek Polacek  <polacek@redhat.com>

	* doc/invoke.texi: Update -Wdangling-reference documentation.

2024-02-01  Uros Bizjak  <ubizjak@gmail.com>

	PR target/113701
	* config/i386/i386.md (*cmp<dwi>_doubleword):
	Do not force SUBREG pieces to pseudos.

2024-02-01  John David Anglin  <danglin@gcc.gnu.org>

	* config/pa/pa.md (atomic_storedi_1): Fix bug in
	alternative 1.

2024-02-01  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc: Tabify.

2024-02-01  Richard Ball  <richard.ball@arm.com>

	PR tree-optimization/111268
	* tree-vect-slp.cc (vectorizable_slp_permutation_1):
	Add variable-length check for vector input arguments
	to a function.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
	hard-code number of SGPR/VGPR/AVGPR registers.
	* config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
	SGPR/VGPR/AVGPR registers.

2024-02-01  Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
	attribute, and include sifive-p600.md.
	* config/riscv/generic-ooo.md: Update type attribute.
	* config/riscv/generic.md: Update type attribute.
	* config/riscv/sifive-7.md: Update type attribute.
	* config/riscv/sifive-p600.md: New file.
	* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
	Add sifive_p600.
	* config/riscv/riscv.cc (sifive_p600_tune_info): New.
	* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
	* doc/invoke.texi (RISC-V Options): Add sifive-p600-series

2024-02-01  Monk Chiang  <monk.chiang@sifive.com>

	* common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
	Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
	* config/riscv/riscv.opt: New macro for 7 new unprivileged
	extensions.
	* doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
	Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.

2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	* config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
	-static-libasan.  Add missing whitespace.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
	(FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
	Don't 'define_constants'.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

	* config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
	[TARGET_RDNA3]: Adjust.

2024-02-01  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113693
	* tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
	data when available.

2024-02-01  Jakub Jelinek  <jakub@redhat.com>
	    Jason Merrill  <jason@redhat.com>

	PR c++/113531
	* gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
	on variables which were promoted to TREE_STATIC.

2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
	    Richard Biener  <rguenther@suse.de>

	PR target/113560
	* tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
	information via tree_non_zero_bits to check if this operand
	is suitably extended for a widening (or highpart) multiplication.
	(convert_mult_to_widen): Insert explicit casts if the RHS or LHS
	isn't already of the claimed type.

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	Revert:
	2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
	(generic_ooo_branch): ditto
	* config/riscv/generic.md (generic_sfb_alu): ditto
	(generic_fmul_half): ditto
	* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
	* config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
	(sifive_7_popcount): ditto
	* config/riscv/vector.md: change rdfrm to fmove
	* config/riscv/zc.md: change pushpop to load/store

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	Revert:
	2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
		    Robin Dapp  <rdapp.gcc@gmail.com>

	* config/riscv/generic-ooo.md (generic_ooo): Move reservation
	(generic_ooo_vec_load): ditto
	(generic_ooo_vec_store): ditto
	(generic_ooo_vec_loadstore_seg): ditto
	(generic_ooo_vec_alu): ditto
	(generic_ooo_vec_fcmp): ditto
	(generic_ooo_vec_imul): ditto
	(generic_ooo_vec_fadd): ditto
	(generic_ooo_vec_fmul): ditto
	(generic_ooo_crypto): ditto
	(generic_ooo_perm): ditto
	(generic_ooo_vec_reduction): ditto
	(generic_ooo_vec_ordered_reduction): ditto
	(generic_ooo_vec_idiv): ditto
	(generic_ooo_vec_float_divsqrt): ditto
	(generic_ooo_vec_mask): ditto
	(generic_ooo_vec_vesetvl): ditto
	(generic_ooo_vec_setrm): ditto
	(generic_ooo_vec_readlen): ditto
	* config/riscv/riscv.md: include generic-vector-ooo
	* config/riscv/generic-vector-ooo.md: New file. to here

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	Revert:
	2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
	    Robin Dapp  <rdapp.gcc@gmail.com>

	* config/riscv/generic-ooo.md (generic_ooo): Move reservation
	(generic_ooo_vec_load): ditto
	(generic_ooo_vec_store): ditto
	(generic_ooo_vec_loadstore_seg): ditto
	(generic_ooo_vec_alu): ditto
	(generic_ooo_vec_fcmp): ditto
	(generic_ooo_vec_imul): ditto
	(generic_ooo_vec_fadd): ditto
	(generic_ooo_vec_fmul): ditto
	(generic_ooo_crypto): ditto
	(generic_ooo_perm): ditto
	(generic_ooo_vec_reduction): ditto
	(generic_ooo_vec_ordered_reduction): ditto
	(generic_ooo_vec_idiv): ditto
	(generic_ooo_vec_float_divsqrt): ditto
	(generic_ooo_vec_mask): ditto
	(generic_ooo_vec_vesetvl): ditto
	(generic_ooo_vec_setrm): ditto
	(generic_ooo_vec_readlen): ditto
	* config/riscv/riscv.md: include generic-vector-ooo
	* config/riscv/generic-vector-ooo.md: New file. to here

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

	* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
	(generic_ooo_branch): ditto
	* config/riscv/generic.md (generic_sfb_alu): ditto
	(generic_fmul_half): ditto
	* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
	* config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
	(sifive_7_popcount): ditto
	* config/riscv/vector.md: change rdfrm to fmove
	* config/riscv/zc.md: change pushpop to load/store

2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/113657
	* config/aarch64/aarch64-simd.md (split for movv8di):
	For strict aligned mode, use DImode instead of TImode.

2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>

	PR middle-end/113607
	* match.pd: Make sure else values match when folding a
	vec_cond into a conditional operation.

2024-01-31  Marek Polacek  <polacek@redhat.com>

	* doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.

2024-01-31  Tamar Christina  <tamar.christina@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	PR sanitizer/112644
	* asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
	memcmp.
	* builtins.cc (expand_builtin): Include HWASAN when checking for
	builtin inlining.

2024-01-31  Richard Biener  <rguenther@suse.de>

	PR middle-end/110176
	* match.pd (zext (bool) <= (int) 4294967295u): Make sure
	to match INTEGER_CST only without outstanding conversion.

2024-01-31  Alex Coplan  <alex.coplan@arm.com>

	PR target/111677
	* config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
	V16QImode for the full 16-byte FPR saves in the vector PCS case.

2024-01-31  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/111444
	* tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
	vn_reference_lookup_2 when optimistically skipping may-defs.

2024-01-31  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113630
	* tree-ssa-pre.cc (compute_avail): Avoid registering a
	reference with a representation with not matching base
	access size.

2024-01-31  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/113656
	* simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
	<case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.

2024-01-31  Jakub Jelinek  <jakub@redhat.com>

	PR debug/113637
	* dwarf2out.cc (loc_list_from_tree_1): Assume integral types
	with BLKmode are larger than DWARF2_ADDR_SIZE.

2024-01-31  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113639
	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
	For VIEW_CONVERT_EXPR set rhs1 to its operand.

2024-01-31  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113670
	* tree-vect-data-refs.cc (vect_check_gather_scatter):
	Make sure we can take the address of the reference base.

2024-01-31  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
	ATA5835, ATtiny64AUTO, ATA5700M322.
	* doc/avr-mmcu.texi: Rebuild.

2024-01-31  Alexandre Oliva  <oliva@adacore.com>

	PR debug/113394
	* ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
	caller.

2024-01-31  Alexandre Oliva  <oliva@adacore.com>

	PR middle-end/112917
	PR middle-end/113100
	* builtins.cc (expand_builtin_stack_address): Use
	STACK_ADDRESS_OFFSET.
	* doc/extend.texi (__builtin_stack_address): Adjust.
	* config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
	* doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
	* doc/tm.texi: Rebuilt.

2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113495
	* config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
	(pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
	(pre_vsetvl::compute_transparent): New function.
	(pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.

2024-01-30  Fangrui Song  <maskray@google.com>

	PR target/105576
	* config/i386/constraints.md: Define constraint "Ws".
	* doc/md.texi: Document it.

2024-01-30  Marek Polacek  <polacek@redhat.com>

	PR c++/110358
	PR c++/109640
	* doc/invoke.texi: Update -Wdangling-reference description.

2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

	* config/xtensa/constraints.md (R, T, U):
	Change define_constraint to define_memory_constraint.
	* config/xtensa/predicates.md (move_operand): Don't check that a
	constant pool operand size is a multiple of UNITS_PER_WORD.
	* config/xtensa/xtensa.cc
	(xtensa_lra_p, TARGET_LRA_P): Remove.
	(xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
	clause as it can no longer be true.
	(fixup_subreg_mem): Drop function.
	(xtensa_output_integer_literal_parts): Consider 16-bit wide
	constants.
	(xtensa_legitimate_constant_p): Add short-circuit path for
	integer load instructions. Don't check that mode size is
	at least UNITS_PER_WORD.
	* config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
	rather reload_in_progress and reload_completed.
	(doloop_end): Drop operand 2.
	(movhi_internal): Add alternative loading constant from a
	literal pool.
	(define_split for DI register_operand): Don't limit to
	!TARGET_AUTO_LITPOOLS.
	* config/xtensa/xtensa.opt (mlra): Change to no effect.

2024-01-30  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
	calculate the gpr count required by vls mode.
	(riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
	(riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
	for vls mode.
	(riscv_get_arg_info): Add vls mode handling.
	(riscv_pass_by_reference): Return false if arg info has no zero gpr count.

2024-01-30  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113659
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Handle main exit without virtual use.

2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.

2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>

	PR libgcc/113403
	* config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
	(REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
	* config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
	* config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
	* config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
	* config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.

2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113623
	* config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
	Mark all registers that occur in addresses as needing a GPR.

2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113636
	* config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
	the containing insn as an extra parameter.  Reset debug instructions
	if they reference a register that is no longer used by real insns.
	(early_ra::apply_allocation): Update calls accordingly.

2024-01-30  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113603
	* tree-ssa-strlen.cc (strlen_pass::handle_store): After
	count_nonzero_bytes call refetch si using get_strinfo in case it
	has been unshared in the meantime.

2024-01-30  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/101195
	* except.cc (expand_builtin_eh_return_data_regno): If which doesn't
	fit into unsigned HOST_WIDE_INT, return constm1_rtx.

2024-01-30  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/thead.cc (th_print_operand_address): Change %ld
	to %lld.

2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
	    Manolis Tsamis  <manolis.tsamis@vrull.eu>
	    Philipp Tomsich  <philipp.tomsich@vrull.eu>

	* config/aarch64/aarch64-ldpstp.md: Remove unused mode.
	* config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
	Likewise.
	* config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
	Call on framework moved later.

2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
	instruction in naked function epilogues.

2024-01-29  YunQiang Su  <syq@gcc.gnu.org>

	PR target/113655
	* configure.ac: Fix typo gcc_cv_as_mips_explicit should be
	gcc_cv_as_mips_explicit_relocs.
	* configure: Regnerated.

2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>

	PR target/108933
	* config/arm/arm.md (arm_rev16si2): Convert to define_insn.
	Correct generated RTL.
	(arm_rev16si2_alt1): Correctly handle conditional execution.
	(arm_rev16si2_alt2): Likewise.

2024-01-29  Richard Biener  <rguenther@suse.de>

	PR middle-end/113622
	* expr.cc (expand_assignment): Spill hard registers if
	we index them with a variable offset.

2024-01-29  Richard Biener  <rguenther@suse.de>

	PR middle-end/113622
	* gimple-isel.cc (gimple_expand_vec_set_extract_expr):
	Also allow DECL_HARD_REGISTER variables.

2024-01-29  Alex Coplan  <alex.coplan@arm.com>

	PR target/113616
	* config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
	Use iterate_safely when iterating over debug uses.
	(fixup_debug_uses): Likewise.
	(ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
	over nondebug insns instead of manually maintaining the next insn.
	* iterator-utils.h (class safe_iterator): New.
	(iterate_safely): New.

2024-01-29  H.J. Lu  <hjl.tools@gmail.com>

	PR target/38534
	* config/i386/i386-options.cc (ix86_set_func_type): Save
	callee-saved registers in noreturn functions for -O0/-Og.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

	PR target/113615
	* config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
	define for !TARGET_RDNA2_PLUS.

2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113281
	* tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
	workaround for right shifts.
	(vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
	(vect_determine_precisions_from_range): Be more selective about
	which codes can be narrowed based on their input and output ranges.
	For shifts, require at least one more bit of precision than the
	maximum shift amount.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

	* config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

	* doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
	but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
	LLVM 13.0.1+.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

	PR other/111966
	* config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
	(SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
	(SET_SRAM_ECC_UNSET): ... this.
	(copy_early_debug_info): Remove gfx900 special case, now handled as
	part of the generic handling.
	(main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.

2024-01-29  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/110603
	* tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
	setting of pdata->maxlen to vr.upper_bound (which is unconditionally
	overwritten anyway).  Avoid creating invalid range with minlen
	larger than maxlen.  Formatting fix.

2024-01-29  Richard Biener  <rguenther@suse.de>

	PR debug/103047
	* tree-inline.cc (initialize_inlined_parameters): Reverse
	the decl chain of inlined parameters.

2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>

	* config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
	alignment of CFString constants by setting DECL_USER_ALIGN.

2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
	    Jakub Jelinek   <jakub@redhat.com>

	PR libgcc/113402
	* builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
	and BUILT_IN_GCC_NESTED_PTR_DELETED.
	* builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
	BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
	rename the library fallbacks to __gcc_nested_func_ptr_created and
	__gcc_nested_func_ptr_deleted.
	* doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
	and __gcc_nested_func_ptr_deleted.
	* tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
	BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
	* tree.cc (build_common_builtin_nodes): Build the
	BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
	builtins only for non-explicit.

2024-01-28  YunQiang Su  <syq@gcc.gnu.org>

	* doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.

2024-01-27  H.J. Lu  <hjl.tools@gmail.com>

	PR target/38534
	* config/i386/i386-options.cc (ix86_set_func_type): Don't
	save and restore callee saved registers for a noreturn function
	with nothrow or compiled with -fno-exceptions.

2024-01-27  H.J. Lu  <hjl.tools@gmail.com>

	PR target/103503
	PR target/113312
	* config/i386/i386-expand.cc (ix86_expand_call): Replace
	no_caller_saved_registers check with call_saved_registers check.
	Clobber all registers that are not used by the callee with
	no_callee_saved_registers attribute.
	* config/i386/i386-options.cc (ix86_set_func_type): Set
	call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
	noreturn function.  Disallow no_callee_saved_registers with
	interrupt or no_caller_saved_registers attributes together.
	(ix86_set_current_function): Replace no_caller_saved_registers
	check with call_saved_registers check.
	(ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
	(ix86_handle_call_saved_registers_attribute): This.
	(ix86_gnu_attributes): Add
	ix86_handle_call_saved_registers_attribute.
	* config/i386/i386.cc (ix86_conditional_register_usage): Replace
	no_caller_saved_registers check with call_saved_registers check.
	(ix86_function_ok_for_sibcall): Don't allow callee with
	no_callee_saved_registers attribute when the calling function
	has callee-saved registers.
	(ix86_comp_type_attributes): Also check
	no_callee_saved_registers.
	(ix86_epilogue_uses): Replace no_caller_saved_registers check
	with call_saved_registers check.
	(ix86_hard_regno_scratch_ok): Likewise.
	(ix86_save_reg): Replace no_caller_saved_registers check with
	call_saved_registers check.  Don't save any registers for
	TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
	TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
	no_callee_saved_registers attribute is called.
	(find_drap_reg): Replace no_caller_saved_registers check with
	call_saved_registers check.
	* config/i386/i386.h (call_saved_registers_type): New enum.
	(machine_function): Replace no_caller_saved_registers with
	call_saved_registers.
	* doc/extend.texi: Document no_callee_saved_registers attribute.

2024-01-27  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113614
	* gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
	widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
	TRUNC_MOD_EXPR or FLOAT_EXPR uses.

2024-01-27  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113568
	* gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
	For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
	in the widening extension checks.

2024-01-27  Jakub Jelinek  <jakub@redhat.com>

	* gimple-lower-bitint.cc (gimple_lower_bitint): For
	TDF_DETAILS dump mapping of SSA_NAMEs to decls.

2024-01-26  Hans-Peter Nilsson  <hp@axis.com>

	* cgraphunit.cc (process_function_and_variable_attributes): Tweak
	the warning for an attribute-always_inline without inline declaration.

2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>

	PR other/113575
	* genopinit.cc (main): Split init_all_optabs into functions
	of 1000 patterns each.

2024-01-26  Tobias Burnus  <tburnus@baylibre.com>

	* config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
	TM_MULTILIB_CONFIG.
	* doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
	* doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
	-march/-mtune.

2024-01-26  Andrew Stubbs  <ams@baylibre.com>

	* config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
	* config/gcn/gcn-valu.md (all_convert): New iterator.
	(<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
	define_expand, and rename the old one to ...
	(*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
	(extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
	(extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
	(*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
	* config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
	(gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
	* config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
	(<u>mulqihi3_scalar): Likewise.

2024-01-26  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113602
	* tree-data-ref.cc (dr_analyze_innermost): Fail when
	the base object isn't addressable.

2024-01-26  Tobias Burnus  <tburnus@baylibre.com>

	* config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
	"--amdhsa-code-object-version=" argument.
	(ASM_SPEC): Use it; replace previous version of it.

2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
	(pre_vsetvl::emit_vsetvl): Ditto.

2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md (vec_extract<mode>_0):
	New define_insn_and_split patten.

2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.

2024-01-26  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.

2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113469
	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.

2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/100212
	* config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
	undefined shift after the call to exact_log2.

2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/100204
	* config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
	before taking the negative of it.

2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR target/113526
	* lra-constraints.cc (curr_insn_transform): Change class even for
	spilled pseudo successfully matched with with NO_REGS.

2024-01-25  Georg-Johann Lay  <avr@gjlay.de>

	PR target/113601
	* config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.

2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	PR target/112987
	* config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
	(aarch64_expand_epilogue): Use the new function.
	(aarch64_split_compare_and_swap): Likewise.
	(aarch64_split_atomic_op): Likewise.

2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>

	PR middle-end/112971
	* fold-const.cc (simplify_const_binop): New function for binop
	simplification of two constant vectors when element-wise
	handling is not necessary.
	(const_binop): Call new function.

2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>

	* common/config/riscv/riscv-common.cc: Add XCVbitmanip.
	* config/riscv/constraints.md: Likewise.
	* config/riscv/corev.def: Likewise.
	* config/riscv/corev.md: Likewise.
	* config/riscv/predicates.md: Likewise.
	* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
	* config/riscv/riscv-ftypes.def: Likewise.
	* config/riscv/riscv.opt: Likewise.
	* config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
	* doc/extend.texi: Add XCVbitmanip builtin documentation.
	* doc/sourcebuild.texi: Likewise.

2024-01-25  Tobias Burnus  <tburnus@baylibre.com>

	* config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.

2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>

	PR target/113538
	* config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
	(riscv_fntype_abi): Ditto.
	* config/riscv/riscv.opt: Ditto.

2024-01-25  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113574
	* convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
	count against TYPE_PRECISION rather than TYPE_SIZE.

2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113572
	* config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
	Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT

2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113550
	* config/aarch64/aarch64-simd.md: In the movv8di splitter, check
	whether each split instruction is a load that clobbers the source
	address.  Emit that instruction last if so.

2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113485
	* config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
	pattern.
	(<optab><Vnarrowq><mode>2): Use it instead of generating a
	paradoxical subreg for the input.

2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
	(pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
	predecessors dump information.

2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
	redundant full available computation.
	(pre_vsetvl::pre_global_vsetvl_info): Ditto.

2024-01-25  Jakub Jelinek  <jakub@redhat.com>

	* doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
	* doc/rtl.texi (CONST_VECTOR): Likewise.

2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
	(pass_vsetvl::execute): Ditto.
	* config/riscv/riscv.opt: Ditto.

2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
	* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.

2024-01-25  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113576
	* tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
	exits with may_be_zero niters when its the last one.

2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
	For symbols of type tls, non-zero Offset is not generated.

2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>

	* config/rs6000/rs6000-string.cc (expand_block_compare): Enable
	P9 with m32 and mpowerpc64.

2024-01-25  liuhongt  <hongtao.liu@intel.com>

	* config/i386/i386-options.cc (ix86_option_override_internal):
	Enable -mlam=u57 by default when compiled with
	-fsanitize=hwaddress.

2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>

	* common/config/riscv/riscv-common.cc (riscv_implied_info):
	Remove {"ztso", "a"}.

2024-01-24  Martin Jambor  <mjambor@suse.cz>

	PR ipa/108007
	PR ipa/112616
	* cgraph.h (cgraph_edge): Add a parameter to
	redirect_call_stmt_to_callee.
	* ipa-param-manipulation.h (ipa_param_adjustments): Add a
	parameter to modify_call.
	(ipa_release_ssas_in_hash): Declare.
	* cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
	parameter killed_ssas, pass it to padjs->modify_call.
	* ipa-param-manipulation.cc (purge_all_uses): New function.
	(ipa_param_adjustments::modify_call): New parameter killed_ssas.
	Instead of substituting uses, invoke purge_all_uses.  If
	hash of killed SSAs has not been provided, create a temporary one
	and release SSAs that have been added to it.
	(compare_ssa_versions): New function.
	(ipa_release_ssas_in_hash): Likewise.
	* tree-inline.cc (redirect_all_calls): Create
	id->killed_new_ssa_names earlier, pass it to edge redirection,
	adjust a comment.
	(copy_body): Release SSAs in id->killed_new_ssa_names.

2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/113486
	* config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
	TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.

2024-01-24  Monk Chiang  <monk.chiang@sifive.com>

	PR target/113095
	* config/riscv/sfb.md: New splitters to rewrite single bit
	sign extension as the condition to SFB instructions.

2024-01-24  Jan Hubicka  <jh@suse.cz>

	PR middle-end/88345
	* common.opt: (flimit-function-alignment): Reorder alphabeticaly
	(fmin-function-alignment): New parameter.
	* doc/invoke.texi: (-fmin-function-alignment): Document.
	(-falign-functions,-falign-loops,-falign-labels): Mention that
	aglinments are ignored in cold code.
	* varasm.cc (assemble_start_function): Handle min-function-alignment.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

	PR target/109636
	* config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
	mulv2di3): Remove.
	* config/aarch64/iterators.md (VQDIV): Remove.
	(SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
	SVE_I_SIMD_DI): New.
	(VPRED, sve_lane_con): Add V4SI and V2DI.
	* config/aarch64/aarch64-sve.md (<optab><mode>3,
	@aarch64_pred_<optab><mode>): Support Advanced SIMD types.
	(mul<mode>3): New, split from <optab><mode>3.
	(@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
	* config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
	*aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
	SVE_FULL_HSDI_SIMD_DI.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113552
	* config/aarch64/aarch64.cc
	(aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.

2024-01-24  Martin Jambor  <mjambor@suse.cz>

	PR ipa/113490
	* ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
	count is equal or greater than the limit.  Use the limit from the
	callee.

2024-01-24  YunQiang Su  <syq@gcc.gnu.org>

	* configure.ac: Detect the explicit relocs support for
	mips, and define C macro MIPS_EXPLICIT_RELOCS.
	* config.in: Regenerated.
	* configure: Regenerated.
	* doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
	* config/mips/mips-opts.h: Define enum mips_explicit_relocs.
	* config/mips/mips.cc(mips_set_compression_mode): Sorry if
	!TARGET_EXPLICIT_RELOCS instead of just set it.
	* config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
	TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
	* config/mips/mips.opt: Introduce -mexplicit-relocs= option
	and define -m(no-)explicit-relocs as aliases.

2024-01-24  Alex Coplan  <alex.coplan@arm.com>

	* config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
	to 1.
	(-mlate-ldp-fusion): Likewise.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

	* tree-vect-loop.cc (vect_get_vect_def,
	vect_create_epilog_for_reduction): Rename main_exit_p to
	last_val_reduc_p.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113364
	* tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
	early exits then we must reduce from the first offset for all of them.

2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113495
	* config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
	(get_regno): Ditto.
	(get_bb_index): Ditto.
	(pre_vsetvl::compute_avl_def_data): Ditto.
	(pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
	(pre_vsetvl::pre_global_vsetvl_info): Ditto.

2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
	    Richard Sandiford  <richard.sandiford@arm.com>

	PR target/100942
	* ccmp.cc (ccmp_candidate_p): Add outer argument.
	Allow if the outer is true and the lhs is used more
	than once.
	(expand_ccmp_expr): Update call to ccmp_candidate_p.
	* expr.h (expand_expr_real_gassign): Declare.
	* expr.cc (expand_expr_real_gassign): New function, split out from...
	(expand_expr_real_1): ...here.
	* cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113089
	* config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
	(fixup_debug_use): New.
	(fixup_debug_uses_trailing_add): New.
	(fixup_debug_uses): New. Use it ...
	(ldp_bb_info::fuse_pair): ... here.
	(try_promote_writeback): Call fixup_debug_uses_trailing_add to
	fix up debug uses of the base register that are affected by
	folding in the trailing add insn.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113089
	* config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
	Update trailing nondebug uses of the base register in the case
	of cancelling writeback.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113089
	* rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
	(debug_insn_use_iterator): New.
	(set_info::first_debug_insn_use): New.
	(set_info::debug_insn_uses): New.
	* rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
	(set_info::first_debug_insn_use): New.
	(set_info::debug_insn_uses): New.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113356
	* config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
	Don't record hazards against the opposite insn in the pair.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113070
	* config/aarch64/aarch64-ldp-fusion.cc
	(struct stp_change_builder): New.
	(decide_stp_strategy): Reanme to ...
	(try_repurpose_store): ... this.
	(ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
	construct stp changes.  Fix up uses when inserting new stp insns.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113070
	* rtl-ssa.h: Include hash-set.h.
	* rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
	new_sets parameter and use it to keep track of new user-created sets.
	(function_info::apply_changes_to_insn): Also call add_def on new sets.
	(function_info::change_insns): Add hash_set to keep track of new
	user-created defs.  Plumb it through.
	* rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
	apply_changes_to_insn.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113070
	* rtl-ssa/accesses.cc (function_info::create_use): New.
	* rtl-ssa/changes.cc (function_info::finalize_new_accesses):
	Ensure new uses end up referring to permanent defs.
	* rtl-ssa/functions.h (function_info::create_use): Declare.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113070
	* rtl-ssa/changes.cc (function_info::change_insns): Split out the call
	to finalize_new_accesses from the backwards placement loop, run it
	forwards in a separate loop.

2024-01-23  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113552
	* tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
	floor_log2 instead of exact_log2 on the number of calls.

2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
	    Jakub Jelinek  <jakub@redhat.com>

	* config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
	decl.

2024-01-23  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Separate single and multi-exit case when creating PHIs between
	the main and epilogue.

2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/112989
	* config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
	MODE_single variants of functions that don't take tuple arguments.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

	PR target/113114
	* config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
	Don't assert recog success, just punt if the writeback pair
	isn't recognized.

2024-01-23  Jakub Jelinek  <jakub@redhat.com>

	* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
	ATTRIBUTE_UNUSED to decl.

2024-01-23  Richard Biener  <rguenther@suse.de>

	PR debug/107058
	* dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
	handle unexpected but bogus DIE contexts when not checking
	enabled.

2024-01-23  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113462
	* fold-const.cc (native_interpret_int): Don't punt if total_bytes
	is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
	(fold_view_convert_expr): Use XALLOCAVEC buffers for types with
	sizes between 129 and 8192 bytes.

2024-01-23  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
	If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
	for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
	(loongarch_call_tls_get_addr): Do not split symbols of
	SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
	EXPLICIT_RELOCS_AUTO.

2024-01-23  Richard Biener  <rguenther@suse.de>

	* alias.cc (known_base_value_p): Remove.
	(find_base_value): Remove PLUS/MINUS handling
	when both operands are not CONST_INT_P.

2024-01-23  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/113255
	* alias.cc (find_base_term): Remove PLUS/MINUS handling
	when both operands are not CONST_INT_P.

2024-01-23  Richard Biener  <rguenther@suse.de>

	PR debug/112718
	* dwarf2out.cc (dwarf2out_finish): Reset all type units
	for the fat part of an LTO compile.

2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>

	* doc/sourcebuild.texi: Add attributes for keywords.

2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>

	PR c++/90463
	* doc/invoke.texi (Warning Options): Correct lists of options
	enabled by -Wall and -Wextra by checking against common.opt
	and c-family/c.opt.

2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/113030
	* config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
	instead of cpu_optaliases.
	(check_arch): Use arch_opt_alias instead of arch_optaliases.

2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
	* config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
	* config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.

2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/109092
	* config/riscv/riscv.md: Use reg instead of subreg.

2024-01-22  Tobias Burnus  <tburnus@baylibre.com>

	PR other/111966
	* config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
	to match the compiler default.
	(simple_object_copy_lto_debug_sections): Never unlink the outfile
	on error as the caller does so.
	(maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
	(main): Likewise. Fix 'mkoffload.dbg.o' cleanup.

2024-01-22  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113373
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Create LC PHIs in the exit blocks where necessary.
	* tree-vect-loop.cc (vectorizable_live_operation): Do not try
	to handle missing LC PHIs.
	(find_connected_edge): Remove.
	(vect_create_epilog_for_reduction): Cleanup use of auto_vec.

2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.

2024-01-22  xuli  <xuli1@eswincomputing.com>

	PR target/113420
	* config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
	(registered_function::overloaded_hash):refactor.
	(resolve_overloaded_builtin):avoid internal ICE.

2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>

	PR target/82420
	PR target/111279
	* calls.cc (emit_library_call_value_1): Pass valid TYPE
	to emit_push_insn.
	* expr.cc (emit_push_insn): Likewise.

2024-01-21  Jeff Law  <jlaw@ventanamicro.com>

	* config/riscv/riscv.cc (riscv_init_cumulative_args): Install
	correcction version of last change.

2024-01-21  Jeff Law  <jlaw@ventanamicro.com>

	* config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
	fix bugs in signature.

2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
	    Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/111267
	* fwprop.cc (fwprop_propagation::profitabe_p): Rename
	profitable_p method to likely_profitable_p.
	(try_fwprop_subst_node): Update call to likely_profitable_p.
	Only bail-out early when !prop.likely_profitable_p for instructions
	that are not single sets.  When comparing costs, bail-out if the
	cost is unchanged and !prop.likely_profitable_p.

2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>

	PR c++/90464
	* doc/invoke.texi (Warning Options): Document that -Wunused-parameter
	isn't enabled by -Wunused unless -Wextra is provided, and that
	-Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
	-Wunused doesn't enable -Wunused-* options documented as behaving
	otherwise, and list them explicitly.

2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>

	PR c/109708
	* doc/invoke.texi (Warning Options): Fix broken example and
	clean up/reorganize the others.  Also describe what the short-form
	options mean.

2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>

	PR c/102998
	* doc/invoke.texi (Option Summary): Add -Warray-parameter.
	(Warning Options): Correct/edit discussion of -Warray-parameter
	to make the first example less confusing, and fill in missing info.

2024-01-20  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113462
	* gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
	Handle rhs1 INTEGER_CST like SSA_NAME.

2024-01-20  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113491
	* tree-switch-conversion.cc (switch_conversion::build_constructors):
	If elt.index has precision higher than sizetype, fold_convert it to
	sizetype.
	(switch_conversion::array_value_type): Return type if type is
	BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
	(switch_conversion::build_arrays): Use unsigned_type_for rather than
	lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
	above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
	higher than sizetype, use sizetype as tidx type and fold_convert the
	subtraction to sizetype.

2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
	(riscv_vector_mode_supported_any_target_p): Ditto.

2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>

	PR target/110934
	* config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
	(TARGET_ZERO_CALL_USED_REGS): Define.

2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>

	PR target/108640
	* config/m68k/m68k.cc (output_andsi3): Use QImode for
	address adjusted for 1-byte RMW access.
	(output_iorsi3): Likewise.
	(output_xorsi3): Likewise.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

	* doc/invoke.texi (RISC-V Options): Add list of supported
	extensions.

2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113495
	* config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
	(RVV_VUNDEF): Ditto.
	* config/riscv/riscv-vsetvl.cc: Add timevar.

2024-01-19  Richard Biener  <rguenther@suse.de>

	PR debug/113488
	* lto-streamer-in.cc (lto_read_tree_1): When there isn't
	an early DIE but there should be, do not pretend there is.

2024-01-19  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113494
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Handle endless loop on exit.  Handle re-allocated PHI.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113464
	* gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
	optimize loads into GIMPLE_ASM stmts.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113463
	* gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
	Only look through NOP_EXPRs if rhs1 doesn't have wider type than
	lhs.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113459
	* tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
	TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
	of SCALAR_INT_TYPE_MODE if type has BLKmode.
	(vn_reference_lookup_3): Likewise.  Formatting fix.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>
	    Richard Biener  <rguenther@suse.de>

	* cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
	VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
	* expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
	but adjust_address also for BLKmode mode and MEM op0.

2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>

	* common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
	extensions.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

	* doc/invoke.texi (RISC-V Options): Document the syntax of -march.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::parse_std_ext): Remove.
	(riscv_subset_list::parse_multiletter_ext): Remove.
	* config/riscv/riscv-subset.h
	(riscv_subset_list::parse_std_ext): Remove.
	(riscv_subset_list::parse_multiletter_ext): Remove.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::parse_single_std_ext): New parameter.
	(riscv_subset_list::parse_single_multiletter_ext): Ditto.
	(riscv_subset_list::parse_single_ext): Ditto.
	(riscv_subset_list::parse): Relax the order for the input of ISA
	string.
	* config/riscv/riscv-subset.h
	(riscv_subset_list::parse_single_std_ext): New parameter.
	(riscv_subset_list::parse_single_multiletter_ext): Ditto.
	(riscv_subset_list::parse_single_ext): Ditto.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::parse_base_ext): New.
	(riscv_subset_list::parse): Extract part of logic into
	riscv_subset_list::parse_base_ext.
	* config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
	New.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

	* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
	sorry message.

2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>

	* config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
	UNSPEC_CLMUL_VC.

2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>

	PR c/110029
	* doc/extend.texi (Common Variable Attributes): Explain what
	happens when multiple variables with cleanups are in the same scope.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

	PR ipa/108470
	* doc/extend.texi (Common Function Attributes): Document that
	noinline also disables some interprocedural optimizations and
	improve flow to the part about using inline asm instead to
	disable calls from being optimized away completely.  Remove the
	sentence that says noipa is mainly for internal compiler testing.

2024-01-18  John David Anglin  <danglin@gcc.gnu.org>

	PR tree-optimization/69807
	* config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.

2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>

	PR target/108521
	* doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
	from x86 Windows Options.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

	PR c/107942
	* doc/extend.texi (C Extensions): Add new section to menu.
	(Function Attributes):  Move dangling index entries to....
	(Const and Volatile Functions): New section.

2024-01-18  David Malcolm  <dmalcolm@redhat.com>

	PR middle-end/112684
	* toplev.cc (toplev::main): Don't ICE in
	-fdiagnostics-generate-patch when exiting after options,
	since no edit context will have been created.

2024-01-18  Richard Biener  <rguenther@suse.de>

	* tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
	operands vector.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

	* Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
	when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/thead.cc
	(th_asm_output_opcode): Rewrite some instructions.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/riscv.md (none,thv,rvv): New attribute.
	(no,yes): Add an attribute to disable alternative
	for xtheadvector or RVV1.0.
	* config/riscv/vector.md:
	Disable alternatives that destination register overlaps
	source register group for xtheadvector.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/riscv-vector-builtins-bases.cc
	(class th_loadstore_width): Define new builtin bases.
	(class th_extract): Define new builtin bases.
	(BASE): Define new builtin bases.
	* config/riscv/riscv-vector-builtins-bases.h:
	Define new builtin class.
	* config/riscv/riscv-vector-builtins-shapes.cc
	(struct th_loadstore_width_def): Define new builtin shapes.
	(struct th_indexed_loadstore_width_def):
	Define new builtin shapes.
	(struct th_extract_def): Define new builtin shapes.
	(SHAPE): Define new builtin shapes.
	* config/riscv/riscv-vector-builtins-shapes.h:
	Define new builtin shapes.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
	Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
	* config/riscv/riscv-vector-builtins.h
	(enum required_ext): Add new XTheadVector member.
	(struct function_group_info): Likewise.
	* config/riscv/t-riscv:
	Add thead-vector-builtins-functions.def
	* config/riscv/thead-vector.md
	(@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
	(*pred_mov_width<vlmem_op_attr><mode>): Likewise.
	(@pred_store_width<vlmem_op_attr><mode>): Likewise.
	(@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
	(@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
	(@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
	(@pred_th_extract<mode>): Likewise.
	(*pred_th_extract<mode>): Likewise.
	* config/riscv/thead-vector-builtins-functions.def: New file.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config.gcc:  Add files for XTheadVector intrinsics.
	* config/riscv/autovec.md: Guard XTheadVector.
	* config/riscv/predicates.md: Disable immediate vl
	for XTheadVector.
	* config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
	Add pragma for XTheadVector.
	* config/riscv/riscv-string.cc (riscv_expand_block_move):
	Guard XTheadVector.
	* config/riscv/riscv-v.cc (vls_mode_valid_p):
	Avoid autovec.
	* config/riscv/riscv-vector-builtins-bases.cc:
	Do not normalize vsetvl instructions for XTheadVector.
	* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
	New check type function.
	(build_one): Adjust for XTheadVector.
	* config/riscv/riscv-vector-switch.def (ENTRY):
	Disable fractional mode for the XTheadVector extension.
	(TUPLE_ENTRY): Likewise.
	* config/riscv/riscv.cc (riscv_v_adjust_bytesize):
	Guard XTheadVector.
	(riscv_preferred_simd_mode): Likewsie.
	(riscv_autovectorize_vector_modes): Likewise.
	(riscv_vector_mode_supported_any_target_p): Likewise.
	(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
	* config/riscv/thead.cc (th_asm_output_opcode):
	Rewrite vsetvl instructions.
	* config/riscv/vector.md:
	Include thead-vector.md and change fractional LMUL
	into 1 for vbool.
	* config/riscv/riscv_th_vector.h: New file.
	* config/riscv/thead-vector.md: New file.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
	Add new function to add assembler insn code prefix/suffix.
	(th_asm_output_opcode):
	Add Thead function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.cc (riscv_asm_output_opcode):
	Implement function to add assembler insn code prefix/suffix.
	* config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
	Add new function to add assembler insn code prefix/suffix.
	* config/riscv/thead.cc (th_asm_output_opcode):
	Implement Thead function to add assembler insn code
	prefix/suffix.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::parse): Add new vendor extension.
	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	Add test marco.
	* config/riscv/riscv.opt:  Add new mask.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

	* config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
	to be conditional on macosx-version-min.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

	* config/darwin.cc (darwin_objc1_section): Use the correct
	meta-data version for constant strings.
	(machopic_select_section): Assert if we fail to handle CFString
	sections as Obejctive-C meta-data or drectly.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

	* lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
	OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
	OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
	versions when the object format is Mach-O.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

	PR target/105522
	* config/darwin.cc (machopic_select_section): Handle C and C++
	CFStrings.
	(darwin_rename_builtins): Move this out of the CFString code.
	(darwin_libc_has_function): Likewise.
	(darwin_build_constant_cfstring): Create an anonymous var to
	hold each CFString.
	* config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
	CFstrings.

2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>

	PR bootstrap/113445
	* haifa-sched.cc (dep_list_size): Make global.
	* sched-deps.cc (find_inc): Use instead of sd_lists_size().
	* sched-int.h (dep_list_size): Declare.

2024-01-18  Martin Jambor  <mjambor@suse.cz>

	PR tree-optimization/110422
	* tree-sra.cc (scan_function): Disqualify bases of operands of asm
	gotos.

2024-01-18  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113475
	* gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
	* gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
	(phi_analyzer::~phi_analyzer): Deallocate and free collected
	phi_grous.
	(phi_analyzer::process_phi): Record allocated phi_groups.

2024-01-18  Richard Biener  <rguenther@suse.de>

	* tree-vect-stmts.cc (vectorizable_store): Do not allocate
	storage for gvec_oprnds elements.

2024-01-18  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
	prefer all later exits we can handle.
	(vect_analyze_loop_form): Free the allocated loop body.
	Adjust comments.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-log.cc: Tabify.

2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/autovec.md: Support vi variant.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-devices.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-c.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/driver-avr.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/gen-avr-mmcu-texi.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/gen-avr-mmcu-specs.cc: Tabify.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	* config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
	minline-strcmp, minline-strncmp, minline-strlen,
	-param=riscv-vector-abi): Remove Bool keywords.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR target/113122
	* config/i386/i386.cc (x86_function_profiler): Add -masm=intel
	support.  Add missing space after , in emitted assembly in some
	cases.  Formatting fixes.

2024-01-18  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/loongarch.md (movsi_internal): Remove
	constraint z.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
	in the diagnostic, and capitalize the device name.
	(print_mcu): Generate specs such that:
	<*check_rodata_in_ram>: New.
	<*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
	<*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
	<*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

	PR other/113399
	* common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
	Common and Optimization.

2024-01-18  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113431
	* tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
	When there is an invariant load we might not preserve
	scalar order.

2024-01-18  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113374
	* tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
	* tree-vect-loop.cc (move_early_exit_stmts): Update
	virtual LC PHIs.
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Refactor.  Preserve virtual LC PHIs on all exits.

2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_split_symbol):
	Assign the '/u' attribute to the mem.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

	PR middle-end/110847
	* doc/invoke.texi (Option Summary): Document negative forms of
	-Wtsan and -Wxor-used-as-pow.
	(Warning Options): Likewise.

2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113429
	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

	* doc/extend.texi (Common Function Attributes): Re-alphabetize
	the table.
	(Common Variable Attributes): Likewise.
	(Common Type Attributes): Likewise.

2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>

	PR middle-end/111659
	* doc/extend.texi (Common Variable Attributes): Fix long lines
	in documentation of strict_flex_array + other minor copy-editing.
	Add a cross-reference to -Wstrict-flex-arrays.
	* doc/invoke.texi (Option Summary): Fix whitespace in tables
	before -fstrict-flex-arrays and -Wstrict-flex-arrays.
	(C Dialect Options): Combine the docs for the two
	-fstrict-flex-arrays forms into a single entry.  Note this option
	is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
	(Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
	Minor copy-editing.  Add cross references to the strict_flex_array
	attribute and -fstrict-flex-arrays option.  Add note that this
	option depends on -ftree-vrp.

2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/113221
	* config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
	only allow REG operands instead of allowing all.

2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>

	* config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
	Remove redundant checks in else condition for readablity.
	(earliest_fuse_vsetvl_info) Print iteration count in debug
	prints.
	(earliest_fuse_vsetvl_info) Fix misleading vsetvl info
	dump details in certain cases.

2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>

	* config/riscv/riscv.opt: New -param=vsetvl-strategy.
	* config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
	* config/riscv/riscv-vsetvl.cc
	(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
	(pass_vsetvl::execute): Use vsetvl_strategy.

2024-01-17  Jan Hubicka  <jh@suse.cz>

	* ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
	accidental hack reseting offset.

2024-01-17  Jan Hubicka  <jh@suse.cz>

	* config/i386/i386-options.cc (ix86_option_override_internal): Fix
	handling of X86_TUNE_AVOID_512FMA_CHAINS.

2024-01-17  Jan Hubicka  <jh@suse.cz>
	    Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/110852
	* predict.cc (expr_expected_value_1): Fix profile merging of PHI and
	binary operations
	(get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
	PRED_COMBINED_VALUE_PREDICTIONS_PHI
	* predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
	(PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113421
	* gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
	comment.
	(bitint_dom_walker::before_dom_children): Add g temporary to simplify
	formatting.  Start at vop rather than cvop even if stmt is a store
	and needs_operand_addr.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113410
	* gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
	If access_nelts is integral with larger precision than sizetype,
	fold_convert it to sizetype.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113408
	* gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
	VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
	to handle_cast.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113406
	* ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
	regardless of whether is_gimple_reg_type (restype) or not.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

	* tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
	funcions -> functions, and use were instead of was.
	* gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
	and guaranteee -> guarantee.
	* attribs.h (struct attr_access): Fix comment typo funcion -> function.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113409
	* omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
	INTEGER_TYPE.
	(omp_extract_for_data): Use build_bitint_type rather than
	build_nonstandard_integer_type if either iter_type or loop->v type
	is BITINT_TYPE.
	* omp-expand.cc (expand_omp_for_generic,
	expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
	BITINT_TYPE like INTEGER_TYPE.

2024-01-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113371
	* tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
	Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
	* tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
	not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.

2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>

	PR rtl-optimization/96388
	PR rtl-optimization/111554
	* sched-deps.cc (find_inc): Avoid exponential behavior.

2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>

	PR c/111693
	* doc/invoke.texi (Option Summary): Move -Wuseless-cast
	from C++ Language Options to Warning Options.  Add entry for
	-Wuse-after-free.
	(C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
	from here....
	(Warning Options): ...to here.  Minor copy-editing to fix typo
	and grammar.

2024-01-17  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.cc (mips_compute_frame_info): If another
	register is used as global_pointer, mark $GP live false.

2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>

	PR target/112973
	* doc/extend.texi (BPF Built-in Functions): Wrap long lines and
	give the section a light copy-editing pass.

2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
	* config/aarch64/aarch64-tune.md: Regenerated.
	* doc/invoke.texi (-mcpu): Add cobalt-100 core.

2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>

	PR target/112573
	* config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
	badly formed CONST expressions.

2024-01-16  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty

2024-01-16  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
	* config/sparc/sync.md (membar_storeload): Turn into named insn
	and add GR712RC errata workaround.
	(membar_v8): Add GR712RC errata workaround.

2024-01-16  Andreas Larsson  <andreas@gaisler.com>

	* config/sparc/sync.md (*membar_storeload_leon3): Remove
	(*membar_storeload): Enable for LEON

2024-01-16  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113372
	PR middle-end/90348
	PR middle-end/110115
	PR middle-end/111422
	* cfgexpand.cc (add_scope_conflicts_2): New function.
	(add_scope_conflicts_1): Use it.

2024-01-16  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
	(avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
	* doc/avr-mmcu.texi: Regenerate.

2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>

	PR tree-optimization/113091
	* tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
	(vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
	scalar use with new function.
	(vect_bb_slp_mark_live_stmts): New function as entry to existing
	overriden functions with same name.
	(vect_slp_analyze_operations): Call new entry function to mark
	live statements.

2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113404
	* config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
	for RVV in big-endian mode.

2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>

	* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
	(riscv_pass_in_vector_p): Delete.
	(riscv_init_cumulative_args): Delete the checking.
	(riscv_get_arg_info): Delete the checking.
	(riscv_function_value): Delete the checking.
	* config/riscv/riscv.h: Delete the member for checking.

2024-01-15  Georg-Johann Lay  <avr@gjlay.de>

	* doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.

2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>

	* config.gcc: Include riscv_bitmanip.h.
	* config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
	* config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
	* config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
	(RISCV_BUILTIN_NO_PREFIX): New helper macro.
	* config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
	* config/riscv/riscv-ftypes.def (2): New ftypes.
	* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
	(RISCV_BUILTIN_NO_PREFIX): Likewise.
	* config/riscv/riscv_bitmanip.h: New file.

2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>

	* config.gcc: Include riscv_crypto.h.
	* config/riscv/riscv_crypto.h: New file.

2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR middle-end/113354
	* lra-constraints.cc (curr_insn_transform): Spill pseudo only used
	in the insn if the corresponding operand does not require hard
	register anymore.

2024-01-15  Georg-Johann Lay  <avr@gjlay.de>

	PR target/107201
	* config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
	* config/avr/driver-avr.cc (avr_no_devlib): New function.
	(avr_devicespecs_file): Use it to remove -nodevicelib from the
	options for cores only.
	* config/avr/avr-arch.h (avr_get_parch): New prototype.
	* config/avr/avr-devices.cc (avr_get_parch): New function.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113247
	* config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
	* config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
	* config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113281
	* config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
	(costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
	* config/riscv/riscv-vector-costs.h: New function.

2024-01-15  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113385
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	First redirect, then split the exit edge.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
	Remove m_num_vector_iterations.
	* config/riscv/riscv-vector-costs.h: Ditto.

2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/113156
	* config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
	(-mbranch-cost): Set "Optimization" flag.

2024-01-15  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113370
	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
	set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
	set it to just prec % limb_prec.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113393
	* config/riscv/vector.md: Fix ternary attributes.

2024-01-14  Georg-Johann Lay  <avr@gjlay.de>

	PR target/112944
	* configure.ac [target=avr]: Check availability of emulations
	avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
	HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
	* configure: Regenerate.
	* config.in: Regenerate.
	* doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
	__AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
	* config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
	* config/avr/avr-arch.h (enum avr_device_specific_features):
	Add AVR_ISA_FLMAP.
	* config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
	AVR_ISA_FLMAP.
	* config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
	(avr_set_core_architecture): Set avr_arch_index.
	(have_avrxmega2_flmap, have_avrxmega4_flmap)
	(have_avrxmega3_rodata_in_flash): Set new static const bool according
	to configure results.
	(avr_rodata_in_flash_p): New function using them.
	(avr_asm_init_sections): Let readonly_data_section->unnamed.callback
	track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
	(avr_asm_named_section): Track avr_has_rodata_p.
	(avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
	and not avr_rodata_in_flash_p ().
	* config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
	(LINK_SPEC): Add %(link_rodata_in_ram).
	(LINK_ARCH_SPEC): Remove.
	* config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
	(have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
	const bool according to configure results.
	(diagnose_mrodata_in_ram): New function.
	(print_mcu): Generate specs with the following changes:
	<*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
	need to extend avr/specs.h each time we add a new bell or whistle.
	<*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
	-m[no-]rodata-in-ram.
	<*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
	<*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
	<*cpp>: Add %(cpp_rodata_in_ram).
	<*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
	requested.
	<*self_spec>: Add -mflmap or %<mflmap as needed.

2024-01-14  Jeff Law  <jlaw@ventanamicro.com>

	* config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
	not the GPR iterator.  Adjust pattern name and mode attribute
	accordingly.

2024-01-13  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113361
	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
	Fix up determination of the type for > limb_prec constants.

2024-01-12  Georg-Johann Lay  <avr@gjlay.de>

	* doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
	Add web-link to the avr-gcc wiki.

2024-01-12  Georg-Johann Lay  <avr@gjlay.de>

	* doc/extend.texi (AVR Variable Attributes) [address]: Remove
	documentation for a version without argument, which is not supported.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
	(vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
	(vld1_f16_x4, vld1_f32_x4): New.
	(vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
	(vld1_bf16_x4): New.
	(vld1q_types_x4): Updated to use vld1q_x4
	from arm_neon_builtins.def
	* config/arm/arm_neon_builtins.def
	(vld1_x4): Updated entries.
	(vld1q_x4): New entries, but comes from the old vld1_x4
	* config/arm/neon.md
	(neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
	(vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
	(vld1_f16_x3, vld1_f32_x3): New.
	(vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
	(vld1_bf16_x3): New.
	(vld1q_types_x3): Updated to use vld1q_x3 from
	arm_neon_builtins.def
	* config/arm/arm_neon_builtins.def
	(vld1_x3): Updated entries.
	(vld1q_x3): New entries, but comes from the old vld1_x2
	* config/arm/neon.md
	(neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
	(vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
	(vld1_f16_x2, vld1_f32_x2): New.
	(vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
	(vld1_bf16_x2): New.
	(vld1q_types_x2): Updated to use vld1q_x2 from
	arm_neon_builtins.def
	* config/arm/arm_neon_builtins.def
	(vld1_x2): Updated entries.
	(vld1q_x2): New entries, but comes from the old vld1_x2
	* config/arm/neon.md
	(neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
	neon_vld1_x2<mode>.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
	(vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
	(vst1q_f16_x4, vst1q_f32_x4): New.
	(vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
	(vst1q_bf16_x4): New.
	* config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
	* config/arm/neon.md
	(neon_vst1q_x4<mode>): New.
	(neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
	* config/arm/unspecs.md
	(UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
	(vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
	(vst1q_f16_x3, vst1q_f32_x3): New.
	(vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
	(vst1q_bf16_x3): New.
	* config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
	* config/arm/neon.md
	(neon_vst1q_x3<mode>): New.
	(neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
	* config/arm/unspecs.md
	(UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
	(vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
	(vst1q_f16_x2, vst1q_f32_x2): New.
	(vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
	(vst1q_bf16_x2): New.
	* config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
	* config/arm/neon.md
	(neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
	neon_vst1_x2<mode>.
	* config/arm/iterators.md
	(VMEMX2): New mode iterator.
	(VMEMX2_q): New mode attribute.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
	(vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
	(vst1_f16_x4, vst1_f32_x4): New.
	(vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
	(vst1_bf16_x4): New.
	* config/arm/arm_neon_builtins.def (vst1_x4): New entries.
	* config/arm/neon.md (vst1_x4<mode>): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
	(vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
	(vst1_f16_x3, vst1_f32_x3): New.
	(vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
	(vst1_bf16_x3): New.
	* config/arm/arm_neon_builtins.def (vst1_x3): New entries.
	* config/arm/neon.md (vst1_x3<mode>): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
	(vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
	(vst1_f16_x2, vst1_f32_x2): New.
	(vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
	(vst1_bf16_x2): New.
	* config/arm/arm_neon_builtins.def (vst1_x2): New entries.
	* config/arm/neon.md (vst1_x2<mode>): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
	(vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
	(vld1q_f16_x4, vld1q_f32_x4): New.
	(vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
	(vld1q_bf16_x4): New.
	* config/arm/arm_neon_builtins.def (vld1_x4): New entries.
	* config/arm/neon.md
	(neon_vld1_x4<mode>): New.
	(neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
	* config/arm/unspecs.md
	(UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
	(vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
	(vld1q_f16_x3, vld1q_f32_x3): New.
	(vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
	(vld1q_bf16_x3): New.
	* config/arm/arm_neon_builtins.def (vld1_x3): New entries.
	* config/arm/neon.md
	(neon_vld1_x3<mode>): New.
	(neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
	* config/arm/unspecs.md
	(UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

	* config/arm/arm_neon.h
	(vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
	(vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
	(vld1q_f16_x2, vld1q_f32_x2): New.
	(vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
	(vld1q_bf16_x2): New.
	* config/arm/arm_neon_builtins.def (vld1_x2): New entries.
	* config/arm/neon.md (vld1_x2<mode>): New.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113287
	* doc/sourcebuild.texi (check_effective_target_bitint65535): New.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

	* tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
	* tree-vect-loop.cc (vect_transform_loop): Likewise.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113178
	* tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
	alternate exits.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113237
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
	existing LCSSA variable for exit when all exits are early break.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113137
	PR tree-optimization/113136
	PR tree-optimization/113172
	PR tree-optimization/113178
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Maintain PHIs on inverted loops.
	(vect_do_peeling): Maintain virtual PHIs on inverted loops.
	* tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
	latch.
	(vect_create_loop_vinfo): Record all conds instead of only alt ones.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113135
	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
	dependency analysis.

2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>

	* config/rs6000/host-darwin.cc (segv_handler): Use the revised
	diagnostics class member name for abort of error.

2024-01-12  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
	format string to %s argument.

2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
	    Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/113182
	* varasm.cc (process_pending_assemble_externals,
	assemble_external_libcall): Use targetm.strip_name_encoding
	before calling get_identifier.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113196
	* config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
	New member variable.
	* config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
	Declare.
	* config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
	* config/aarch64/aarch64-simd.md
	(vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
	(vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
	zip2 for zero-extends to...
	(aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
	instruction.  Fix big-endian handling.
	(vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
	(vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
	zip1 for zero-extends to...
	(<optab><Vnarrowq><mode>2): ...a split of this instruction.
	Fix big-endian handling.
	(*aarch64_zip1_uxtl): New pattern.
	(aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
	(aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
	* config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
	(aarch64_gen_shareable_zero): Use it.
	(aarch64_split_simd_shift_p): New function.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

	* emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
	(function_beg_insn): New macro.
	* function.cc (expand_function_start): Initialize function_beg_insn.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/112989
	* config/aarch64/aarch64-sve-builtins.h
	(function_builder::m_overload_names): Replace with...
	* config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
	new global.
	(add_overloaded_function): Update accordingly, using get_identifier
	to get a GGC-friendly record of the name.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/112989
	* config/aarch64/aarch64-sve-builtins.def: Don't include
	aarch64-sve-builtins-sme.def.
	(DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
	* config/aarch64/aarch64-sve-builtins-sme.def: ...here.
	(DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
	instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
	requires AARCH64_FL_SME2.
	* config/aarch64/aarch64-sve-builtins-sve2.def: Make same
	AARCH64_FL_SME adjustment here.
	* config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
	include SME intrinsics.
	(sme_function_groups): New array.
	(handle_arm_sve_h): Remove check for AARCH64_FL_SME.
	(handle_arm_sme_h): Use sme_function_groups instead of function_groups.

2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113281
	* config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
	(struct cpu_vector_cost): Add regmove struct.
	(get_vector_costs): Export as global.
	* config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
	(costs::add_stmt_cost): Ditto.
	* config/riscv/riscv.cc (get_common_costs): Export global function.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113334
	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
	wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
	to determine if number should be extended by all ones rather than zero
	extended.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113330
	* tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
	too large size.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113323
	* gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
	check for lhs being large/huge _BitInt not in m_names.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113316
	* gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
	uninitialized large/huge _BitInt arguments to calls.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

	* gimple-lower-bitint.cc (mergeable_op): Instead of comparing
	TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
	CEIL (TYPE_PRECISION (t), limb_prec).
	(bitint_large_huge::handle_cast): Likewise.

2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>

	PR sanitizer/113284
	* config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
	Use assemble_function_label_final () for Power ELF V1 ABI.
	* output.h (assemble_function_label_final): New function.
	* varasm.cc (assemble_function_label_raw): Use
	assemble_function_label_final ().
	(assemble_function_label_final): New function.

2024-01-12  Richard Biener  <rguenther@suse.de>

	PR middle-end/113344
	* match.pd ((double)float CMP (double)float -> float CMP float):
	Perform result type check only for vectors.
	* fold-const.cc (fold_binary_loc): Likewise.

2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>

	* config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
	(usdot_prod<mode>): Ditto.
	(sdot_prod<mode>): Ditto.
	(udot_prod<mode>): Ditto.

2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>

	PR target/113288
	* config/i386/i386-c.cc (ix86_target_macros_internal):
	Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.

2024-01-12  Richard Biener  <rguenther@suse.de>

	PR target/112280
	* config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
	Do not generate code when d.testing_p.

2024-01-12  liuhongt  <hongtao.liu@intel.com>

	PR target/113039
	* doc/invoke.texi (fcf-protection=): Update documents.

2024-01-12  Pan Li  <pan2.li@intel.com>

	* config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
	comments of predicate func riscv_v_ext_mode_p.

2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
			Modify ABI-name length of vfloat16m8_t

2024-01-12  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
	Adjust.

2024-01-12  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.md (add<mode>3): Removed.
	(*addsi3): New.
	(addsi3): Ditto.
	(adddi3): Ditto.
	(*addsi3_extended): Removed.
	(addsi3_extended): New.

2024-01-11  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/thead.md: Add limits for splits.

2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/113322
	* expr.cc (do_store_flag): Don't try single bit tests with
	comparison on vector types.

2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/113301
	* match.pd (`1/x`): Delay signed case until late.

2024-01-11  Georg-Johann Lay  <avr@gjlay.de>

	* doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
	and -msp8 to...
	(AVR Internal Options): ...this new @subsubsection.

2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/112918
	* lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
	(in_class_p): Restrict condition for narrowing class in case of
	allow_all_reload_class_changes_p.
	(process_alt_operands): Try to match operand without and with
	narrowing reg class.  Discourage narrowing the class.  Finish insn
	matching only if there is no class narrowing.
	(curr_insn_transform): Pass true to in_class_p for reg operand win.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/112505
	* tree-vect-loop.cc (vectorizable_induction): Reject
	bit-precision induction.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113126
	* match.pd ((double)float CMP (double)float -> float CMP float):
	Make sure the boolean type is the same.
	* fold-const.cc (fold_binary_loc): Likewise.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/112636
	* tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
	estimate_numbers_of_iterations before querying
	get_max_loop_iterations_int.
	(pass_ch::execute): Initialize SCEV and loops appropriately.

2024-01-11  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
	Reduced Tiny.
	* config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
	* doc/extend.texi (AVR Variable Attributes): Improve documentation
	of io, io_low and address attributes.
	* doc/invoke.texi (AVR Options): Add some anchors for external refs.
	* doc/avr-mmcu.texi: Rebuild.

2024-01-11  Yang Yujie  <yangyujie@loongson.cn>

	PR target/113233
	* config/loongarch/genopts/loongarch.opt.in: Mark options with
	the "Save" property.
	* config/loongarch/loongarch.opt: Same.
	* config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
	according to la_target.
	* config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
	RESTORE} for the la_target structure; Rename option conditions
	to have the same "la_" prefix.
	* config/loongarch/loongarch.h: Same.

2024-01-11  Pan Li  <pan2.li@intel.com>

	* loop-unroll.cc (insert_var_expansion_initialization): Leverage
	MODE_HAS_SIGNED_ZEROS for expansion variable initialization.

2024-01-11  Alex Coplan  <alex.coplan@arm.com>

	PR target/113077
	* config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
	fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
	(combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
	synthesize these if needed.  Update caller ...
	(ldp_bb_info::fuse_pair): ... here.
	(ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
	and either insn is frame-related.
	(find_trailing_add): Punt on frame-related insns.
	* config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
	REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.

2024-01-11  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.cc (mips_start_function_definition):
	Add ATTRIBUTE_UNUSED.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR middle-end/112740
	* expr.cc (store_constructor): Check the integer vector
	mask has a single bit per element before using sign-extension
	to expand an uniform vector.

2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
	preempt VLS on unknown NITERS loop.

2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>

	* doc/invoke.texi: Add -mevex512.

2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
	(*nor<mode>3): Likewise.
	(nor<mode>3): Likewise.
	(*negsi2_extended): New template.
	(*<optab>si3_internal): Likewise.
	(*one_cmplsi2_internal): Likewise.
	(*norsi3_internal): Likewise.
	(*<optab>nsi_internal): Likewise.
	(bytepick_w_<bytepick_imm>_extend): Modify this template according to the
	modified bit operation to make the optimization work.

2024-01-11  liuhongt  <hongtao.liu@intel.com>

	PR target/104401
	* match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
	(get_vector_costs): Ditto.
	(riscv_builtin_vectorization_cost): Ditto.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.

2024-01-10  Antoni Boucher  <bouanto@zoho.com>

	PR jit/111396
	* ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
	ipa_free_size_summary.
	* ipa-icf.cc (ipa_icf_cc_finalize): New function.
	* ipa-profile.cc (ipa_profile_cc_finalize): New function.
	* ipa-prop.cc (ipa_prop_cc_finalize): New function.
	* ipa-prop.h (ipa_prop_cc_finalize): New function.
	* ipa-sra.cc (ipa_sra_cc_finalize): New function.
	* ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
	ipa_sra_cc_finalize): New functions.
	* toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
	ipa_prop_cc_finalize, ipa_profile_cc_finalize and
	ipa_sra_cc_finalize
	Include ipa-utils.h.

2024-01-10  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
	(th_int_get_save_adjustment): Likewise.
	(th_int_adjust_cfi_prologue): Likewise.
	* config/riscv/riscv.cc (BITSET_P): Moved away from here.
	(TH_INT_INTERRUPT): New macro.
	(riscv_expand_prologue): Add the processing of XTheadInt.
	(riscv_expand_epilogue): Likewise.
	* config/riscv/riscv.h (BITSET_P): Moved to here.
	* config/riscv/riscv.md: New unspec.
	* config/riscv/thead.cc (th_int_get_mask): New function.
	(th_int_get_save_adjustment): Likewise.
	(th_int_adjust_cfi_prologue): Likewise.
	* config/riscv/thead.md (th_int_push): New pattern.
	(th_int_pop): new pattern.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/112468
	* doc/sourcebuild.texi: Document ifn_copysign.
	* match.pd: Only apply transformation if target supports the IFN.

2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/112581
	* gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
	mark_ssa_maybe_undefs.
	* tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
	variables can not be reassociated.
	(init_range_entry): Check for uninitialized variables too.
	(init_reassoc): Call mark_ssa_maybe_undefs.

2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>

	* config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
	Also handle sign extension.

2024-01-10  Alex Coplan  <alex.coplan@arm.com>

	* config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
	to 0.
	(-mlate-ldp-fusion): Likewise.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113287
	* tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
	instead of using BRANCH_EDGE to determine true edge.

2024-01-10  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113078
	* tree-vect-loop.cc (check_reduction_path): Canonicalize
	.COND_SUB to .COND_ADD.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

	* gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
	Handle prefix mappings before calling find_opt.
	(selftest::gcc_urlifier_cc_tests): Add example of urlifying a
	"-fno-"-prefixed command-line option.
	* opts-common.cc (get_option_prefix_remapping): New.
	* opts.h (get_option_prefix_remapping): New decl.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic.cc (diagnostic_context::report_diagnostic): Pass
	m_urlifier to pp_output_formatted_text.
	* pretty-print.cc: Add #define of INCLUDE_VECTOR.
	(obstack_append_string): New overload, taking a length.
	(urlify_quoted_string): Pass in an obstack ptr, rather than using
	that of the pp's buffer.  Generalize to handle trailing text in
	the buffer beyond the run of quoted text.
	(class quoting_info): New.
	(on_begin_quote): New.
	(on_end_quote): New.
	(pp_format): Refactor phase 1 and phase 2 quoting support, moving
	it to calls to on_begin_quote and on_end_quote.
	(struct auto_obstack): New.
	(quoting_info::handle_phase_3): New.
	(pp_output_formatted_text): Add urlifier param.  Use it if there
	is deferred urlification.  Delete m_quotes.
	(selftest::pp_printf_with_urlifier): Pass urlifier to
	pp_output_formatted_text.
	(selftest::test_urlification): Update results for the existing
	case of quoted text stradding chunks; add more such test cases.
	* pretty-print.h (class quoting_info): New forward decl.
	(chunk_info::m_quotes): New field.
	(pp_output_formatted_text): Add optional urlifier param.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

	* pretty-print.cc (selftest::test_pp_format): Add selftest
	coverage for numbered args.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113144
	PR tree-optimization/113145
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Update all BB that the original exits dominated.

2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>

	* dwarf2out.cc (modified_type_die): Extend the support of reverse
	storage order to enumeration types if -gstrict-dwarf is not passed.
	(gen_enumeration_type_die): Add REVERSE parameter and generate the
	DIE immediately after the existing one if it is true.
	(gen_tagged_type_die): Add REVERSE parameter and pass it in the
	call to gen_enumeration_type_die.
	(gen_type_die_with_usage): Add REVERSE parameter and pass it in the
	first recursive call as well as the call to gen_tagged_type_die.
	(gen_type_die): Add REVERSE parameter and pass it in the call to
	gen_type_die_with_usage.

2024-01-10  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113120
	* tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
	with root->size TYPE_PRECISION don't build anything new.
	Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
	rather than build_nonstandard_integer_type.

2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>

	* config/i386/i386.opt: Adjust document.
	* doc/invoke.texi: Add description for
	-mapx-inline-asm-use-gpr32.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
	(avg<v_double_trunc>3_floor): New pattern.
	(<u>avg<v_double_trunc>3_ceil): Remove.
	(avg<v_double_trunc>3_ceil): New pattern.
	(uavg<mode>3_floor): Ditto.
	(uavg<mode>3_ceil): Ditto.
	* config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
	(enum insn_type): Ditto.
	* config/riscv/riscv-v.cc: Ditto.
	* config/riscv/vector-iterators.md (ashiftrt): Remove.
	(ASHIFTRT): Ditto.
	* config/riscv/vector.md: Add VLS modes.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

	PR target/111480
	* config/rs6000/vsx.md (VCZLSBB): New int iterator.
	(vczlsbb_char): New int attribute.
	(vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
	(vc<vczlsbb_char>zlsbb_<mode>): ... this.
	(*vctzlsbb_zext_<mode>): Rename to ...
	(*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
	cover vclzlsbb.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

	PR target/112606
	* config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
	of the last argument from altivec_register_operand to any_operand.  If
	operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
	otherwise if it doesn't satisfy altivec_register_operand, force it to
	REG using copy_to_mode_reg.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

	PR middle-end/113100
	* builtins.cc (expand_builtin_stack_address): Guard stack point
	adjustment with SPARC_STACK_BOUNDARY_HACK.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
	argument string definitions.
	* config/loongarch/loongarch-str.h: Same.
	* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
	as aliases to -mexplicit-relocs={always,none}
	* config/loongarch/loongarch.opt: Regenerate.
	* config/loongarch/loongarch.cc: Same.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/loongarch-def.h: Define constants with
	enums instead of Macros.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/loongarch-strings: Rename.
	* config/loongarch/genopts/loongarch.opt.in: Same.
	* config/loongarch/loongarch-cpu.cc: Same.
	* config/loongarch/loongarch-def.cc: Same.
	* config/loongarch/loongarch-def.h: Same.
	* config/loongarch/loongarch-opts.cc: Same.
	* config/loongarch/loongarch-opts.h: Same.
	* config/loongarch/loongarch-str.h: Same.
	* config/loongarch/loongarch.opt: Same.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
	variable with the common la_ prefix.
	* config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
	flags as saved using TargetVariable.
	* config/loongarch/loongarch.opt: Same.
	* config/loongarch/loongarch-def.h: Define evolution_set to
	mark changes to the -march default.
	* config/loongarch/loongarch-driver.cc: Same.
	* config/loongarch/loongarch-opts.cc: Same.
	* config/loongarch/loongarch-opts.h: Define and use ISA evolution
	conditions around the la_target structure.
	* config/loongarch/loongarch.cc: Same.
	* config/loongarch/loongarch.md: Same.
	* config/loongarch/loongarch-builtins.cc: Same.
	* config/loongarch/loongarch-c.cc: Same.
	* config/loongarch/lasx.md: Same.
	* config/loongarch/lsx.md: Same.
	* config/loongarch/sync.md: Same.

2024-01-09  Jeff Law  <jlaw@ventanamicro.com>

	* config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
	no less.

2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>

	* config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

	* tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
	restart_loop.
	(vectorizable_live_operation): Likewise.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113199
	* tree-vect-loop.cc (vectorizable_live_operation_1): Use
	BIT_FIELD_REF.

2024-01-09  Jakub Jelinek  <jakub@redhat.com>

	PR target/113270
	* config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
	* config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
	GTY(()) declaration before the definition, drop GTY(()) drom the
	definition.

2024-01-09  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113026
	* tree-vect-loop-manip.cc (vect_do_peeling): Remove
	redundant and wrong niter bound setting.  Move niter
	bound adjustment down.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

	PR middle-end/113163
	* tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
	Reject non-linear inductions that aren't supported.

2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>

	* config/arc/arc.cc (arc_shift_alg): New enumerated type for
	left shift implementation strategies.
	(arc_shift_info): Type for each entry of the shift strategy table.
	(arc_shift_context_idx): Return a integer value for each code
	generation context, used as an index
	(arc_ashl_alg): Table indexed by context and shifted bit count.
	(arc_split_ashl): Use the arc_ashl_alg table to select SImode
	left shift implementation.
	(arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
	provide accurate costs, when optimizing for speed or size.

2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.

2024-01-09  Julian Brown  <julian@codesourcery.com>

	* gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
	processed out before gimplification.
	* tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
	* tree.def (OMP_ARRAY_SECTION): New tree code.

2024-01-09  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113210
	* tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
	value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
	INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
	minus 1.

2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>

	PR rtl-optimization/113140
	* reorg.cc (fill_slots_from_thread): If we are to branch after the
	last instruction of the function, create an end label.

2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
	    Hongtao Liu  <hongtao.liu@intel.com>

	PR target/112992
	* config/i386/i386-expand.cc
	(ix86_convert_const_wide_int_to_broadcast): Allow call to
	ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
	(ix86_broadcast_from_constant): Revert recent change; Return a
	suitable MEMREF independently of mode/target combinations.
	(ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
	to decide whether expansion is possible/preferrable.  Only try
	forcing DImode constants to memory (and trying again) if calling
	ix86_expand_vector_init_duplicate fails with an DImode immediate
	constant.
	(ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
	V4SImode for suitable immediate constants.
	<case E_V4DImode>: Try using V8SImode for suitable constants.
	<case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
	<case E_V2HImode>: Likewise.
	<case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
	<case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
	<label widen>: Handle CONT_INTs via simplify_binary_operation.
	Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
	<case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
	<case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
	(ix86_expand_vector_init): Move try using a broadcast for all_same
	with ix86_expand_vector_init_duplicate before using constant pool.

2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>

	* doc/invoke.texi (Arm Options): Document Cortex-M52 options.

2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>

	* config/arm/arm-cpus.in (cortex-m52): New cpu.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.

2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
	(vec_init<mode><lasxhalf>): .. this, and extend to mode.
	(@vec_concatz<mode>): New insn pattern.
	* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
	Handle VALS containing two vectors.

2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
	(vundefined): Ditto.

2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
				Add new function_base for crypto vector.
	(class bitmanip): Ditto.
	(class b_reverse):Ditto.
	(class vwsll):   Ditto.
	(class clmul):   Ditto.
	(class vg_nhab):  Ditto.
	(class crypto_vv):Ditto.
	(class crypto_vi):Ditto.
	(class vaeskf2_vsm3c):Ditto.
	(class vsm3me): Ditto.
	(BASE): Add BASE declaration for crypto vector.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
				Add crypto vector intrinsic definition.
	(vbrev): Ditto.
	(vclz): Ditto.
	(vctz): Ditto.
	(vwsll): Ditto.
	(vandn): Ditto.
	(vbrev8): Ditto.
	(vrev8): Ditto.
	(vrol): Ditto.
	(vror): Ditto.
	(vclmul): Ditto.
	(vclmulh): Ditto.
	(vghsh): Ditto.
	(vgmul): Ditto.
	(vaesef): Ditto.
	(vaesem): Ditto.
	(vaesdf): Ditto.
	(vaesdm): Ditto.
	(vaesz): Ditto.
	(vaeskf1): Ditto.
	(vaeskf2): Ditto.
	(vsha2ms): Ditto.
	(vsha2ch): Ditto.
	(vsha2cl): Ditto.
	(vsm4k): Ditto.
	(vsm4r): Ditto.
	(vsm3me): Ditto.
	(vsm3c): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
				Add new function_shape for crypto vector.
	(struct crypto_vi_def): Ditto.
	(struct crypto_vv_no_op_type_def): Ditto.
	(SHAPE): Add SHAPE declaration of crypto vector.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data type for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(vuint32mf2_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	(vuint64m1_t): Ditto.
	(vuint64m2_t): Ditto.
	(vuint64m4_t): Ditto.
	(vuint64m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data struct for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
	* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>

	PR sanitizer/113251
	* varasm.cc (assemble_function_label_raw): Do not call
	asan_function_start () without the current function.

2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>

	PR target/113225
	* btfout.cc (btf_collect_datasec): Skip creating BTF info for
	extern and kernel_helper attributed function decls.

2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* btfout.cc (output_btf_strs): Changed.

2024-01-08  Tobias Burnus  <tobias@codesourcery.com>

	* config/gcn/mkoffload.cc (main): Handle gfx1100
	when setting the default XNACK.

2024-01-08  Tobias Burnus  <tobias@codesourcery.com>

	* config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
	* config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
	(ASM_SPEC): Handle gfx1100.
	* config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
	(enum gcn_isa): Add ISA_RDNA3.
	(TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
	* config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
	* config/gcn/gcn.cc (gcn_option_override,
	gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
	(gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
	TARGET_RDNA2 to TARGET_RDNA2_PLUS.
	(gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
	with gfx1100.
	* config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
	(TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
	__gfx1100__.
	* config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
	* config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
	* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
	(isa_has_combined_avgprs, main): Handle gfx1100.
	* config/gcn/t-omp-device (isa): Add gfx1100.

2024-01-08  Richard Biener  <rguenther@suse.de>

	* doc/invoke.texi (-mmovbe): Clarify.

2024-01-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113026
	* tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
	Avoid an epilog in more cases.
	* tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
	epilogues niter upper bounds and estimates.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113228
	* gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113120
	* gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
	large _BitInt zero INTEGER_CST PHI argument.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113119
	* gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
	both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
	is before REALPART_EXPR.

2024-01-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/112952
	* config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
	range when diagnosing attribute "io" and "io_low" are out of range.
	(avr_eval_addr_attrib): Don't ICE on empty address at that place.
	(avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
	in contexts other than static storage.
	(avr_asm_output_aligned_decl_common): Move output of decls with
	attribute "address", "io", and "io_low" to...
	(avr_output_addr_attrib): ...this new function.
	(avr_asm_asm_output_aligned_bss): Remove output for decls with
	attribute "address", "io", and "io_low".
	(avr_encode_section_info): Rectify handling of decls with attribute
	"address", "io", and "io_low".

2024-01-08  Andrew Stubbs  <ams@codesourcery.com>

	* config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
	(elf_flags): Remove XNACK from the default value.
	(main): Set a default XNACK according to the arch.

2024-01-08  Andrew Stubbs  <ams@codesourcery.com>

	* config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
	(process_asm): Don't count avgprs.

2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>

	* config/i386/i386.opt: Add supported sub-features.
	* doc/extend.texi: Add description for target attribute.

2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.

2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
	    Uros Bizjak  <ubizjak@gmail.com>

	PR target/113231
	* config/i386/i386-features.cc (compute_convert_gain): Include
	the overhead of explicit load and store (movd) instructions when
	converting non-store scalar operations with memory destinations.
	Various indentation whitespace fixes.

2024-01-07  Tamar Christina  <tamar.christina@arm.com>

	* config/arm/neon.md (cbranch<mode>4): New.

2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc: replace std::max by MAX.

2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113248
	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
	Update the MAX_SEW.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
	(variable_vectorized_p): Teach loop invariant.
	(has_unexpected_spills_p): Ditto.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
	* config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
	* config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.

2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113104
	* doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
	(aarch64-vect-compare-costs): ...this.
	* config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
	Replace with...
	(-param=aarch64-vect-compare-costs=): ...this new param.
	* config/aarch64/aarch64.cc (aarch64_override_options_internal):
	Don't disable it when vectorizing for Advanced SIMD only.
	(aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
	whenever aarch64_vect_compare_costs is true.

2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
	Modify the method of determining the memory offset of [x]vld/[x]vst.
	(lasx_mxst_<lasxfmt_f>): Likewise.
	* config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
	(loongarch_address_insns): Likewise.
	* config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
	(lsx_st_<lsxfmt_f>): Likewise.
	* config/loongarch/predicates.md (aq10b_operand): Likewise.
	(aq10h_operand): Likewise.
	(aq10w_operand): Likewise.
	(aq10d_operand): Likewise.

2024-01-05  Alex Coplan  <alex.coplan@arm.com>

	PR target/113217
	* config/aarch64/aarch64-ldp-fusion.cc
	(ldp_bb_info::try_fuse_pair): If the second access can throw,
	narrow the move range to exactly that insn.

2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>

	* asan.cc (asan_function_start): Drop switch_to_section ().
	(asan_emit_stack_protection): Set .LASANPC alignment.
	* config/i386/i386.cc: Use assemble_function_label_raw ()
	instead of ASM_OUTPUT_LABEL ().
	* config/s390/s390.cc (s390_asm_output_function_label):
	Likewise.
	* defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
	* final.cc (final_start_function_1): Drop
	asan_function_start ().
	* output.h (assemble_function_label_raw): New function.
	* varasm.cc (assemble_function_label_raw): Likewise.

2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>

	* config/aarch64/aarch64.cc (aarch64_declare_function_name):
	Use ASM_OUTPUT_FUNCTION_LABEL ().
	* config/alpha/alpha.cc (alpha_start_function): Likewise.
	* config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
	* config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
	* config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/ia64/ia64.cc (ia64_start_function): Likewise.
	* config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
	Likewise.
	* config/microblaze/microblaze.cc (microblaze_function_prologue):
	Likewise.
	* config/mips/mips.cc (mips_start_unique_function): Return the
	tree.
	(mips_start_function_definition): Use
	ASM_OUTPUT_FUNCTION_LABEL ().
	(mips_finish_stub): Pass the tree to
	mips_start_function_definition ().
	(mips16_build_function_stub): Likewise.
	(mips16_build_call_stub): Likewise.
	(mips_output_function_prologue): Likewise.
	* config/pa/pa.cc (pa_output_function_label): Use
	ASM_OUTPUT_FUNCTION_LABEL ().
	* config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
	* config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
	Likewise.
	(rs6000_xcoff_declare_function_name): Likewise.

2024-01-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113201
	* tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
	replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.

2024-01-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/90693
	* tree-ssa-math-opts.cc (match_single_bit_test): If
	tree_expr_nonzero_p (arg), remember it in the second argument to
	IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
	arg ^ (arg - 1) > arg - 1.
	* internal-fn.cc (expand_POPCOUNT): If second argument to
	IFN_POPCOUNT suggests arg is non-zero, try to expand it as
	arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.

2024-01-05  Kito Cheng  <kito.cheng@sifive.com>

	* config/riscv/riscv-v.cc (expand_load_store):
	Remove `value`.
	(expand_cond_len_op): Ditto.
	(expand_gather_scatter): Ditto.
	(expand_lanes_load_store): Ditto.
	(expand_fold_extract_last): Ditto.

2024-01-05  Pan Li  <pan2.li@intel.com>

	Revert:
	2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
				Add new function_base for crypto vector.
	(class bitmanip): Ditto.
	(class b_reverse):Ditto.
	(class vwsll):   Ditto.
	(class clmul):   Ditto.
	(class vg_nhab):  Ditto.
	(class crypto_vv):Ditto.
	(class crypto_vi):Ditto.
	(class vaeskf2_vsm3c):Ditto.
	(class vsm3me): Ditto.
	(BASE): Add BASE declaration for crypto vector.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
				Add crypto vector intrinsic definition.
	(vbrev): Ditto.
	(vclz): Ditto.
	(vctz): Ditto.
	(vwsll): Ditto.
	(vandn): Ditto.
	(vbrev8): Ditto.
	(vrev8): Ditto.
	(vrol): Ditto.
	(vror): Ditto.
	(vclmul): Ditto.
	(vclmulh): Ditto.
	(vghsh): Ditto.
	(vgmul): Ditto.
	(vaesef): Ditto.
	(vaesem): Ditto.
	(vaesdf): Ditto.
	(vaesdm): Ditto.
	(vaesz): Ditto.
	(vaeskf1): Ditto.
	(vaeskf2): Ditto.
	(vsha2ms): Ditto.
	(vsha2ch): Ditto.
	(vsha2cl): Ditto.
	(vsm4k): Ditto.
	(vsm4r): Ditto.
	(vsm3me): Ditto.
	(vsm3c): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
				Add new function_shape for crypto vector.
	(struct crypto_vi_def): Ditto.
	(struct crypto_vv_no_op_type_def): Ditto.
	(SHAPE): Add SHAPE declaration of crypto vector.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data type for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(vuint32mf2_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	(vuint64m1_t): Ditto.
	(vuint64m2_t): Ditto.
	(vuint64m4_t): Ditto.
	(vuint64m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data struct for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
	* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
				Add new function_base for crypto vector.
	(class bitmanip): Ditto.
	(class b_reverse):Ditto.
	(class vwsll):   Ditto.
	(class clmul):   Ditto.
	(class vg_nhab):  Ditto.
	(class crypto_vv):Ditto.
	(class crypto_vi):Ditto.
	(class vaeskf2_vsm3c):Ditto.
	(class vsm3me): Ditto.
	(BASE): Add BASE declaration for crypto vector.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
				Add crypto vector intrinsic definition.
	(vbrev): Ditto.
	(vclz): Ditto.
	(vctz): Ditto.
	(vwsll): Ditto.
	(vandn): Ditto.
	(vbrev8): Ditto.
	(vrev8): Ditto.
	(vrol): Ditto.
	(vror): Ditto.
	(vclmul): Ditto.
	(vclmulh): Ditto.
	(vghsh): Ditto.
	(vgmul): Ditto.
	(vaesef): Ditto.
	(vaesem): Ditto.
	(vaesdf): Ditto.
	(vaesdm): Ditto.
	(vaesz): Ditto.
	(vaeskf1): Ditto.
	(vaeskf2): Ditto.
	(vsha2ms): Ditto.
	(vsha2ch): Ditto.
	(vsha2cl): Ditto.
	(vsm4k): Ditto.
	(vsm4r): Ditto.
	(vsm3me): Ditto.
	(vsm3c): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
				Add new function_shape for crypto vector.
	(struct crypto_vi_def): Ditto.
	(struct crypto_vv_no_op_type_def): Ditto.
	(SHAPE): Add SHAPE declaration of crypto vector.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data type for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(vuint32mf2_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	(vuint64m1_t): Ditto.
	(vuint64m2_t): Ditto.
	(vuint64m4_t): Ditto.
	(vuint64m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data struct for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
	* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/113186
	* gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
	Match `^` with the `==` for 1bit integral types.
	* match.pd (maybe_cmp): Allow for bit_xor for 1bit
	integral types.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* toplev.cc (general_init): Pass lang_mask to urlifier.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
	param.
	(diagnostic_context::make_option_url): Update for lang_mask param.
	* gcc-urlifier.cc: Include "opts.h" and "options.h".
	(gcc_urlifier::gcc_urlifier): Add lang_mask param.
	(gcc_urlifier::m_lang_mask): New field.
	(doc_urls): Make static.
	(gcc_urlifier::get_url_for_quoted_text): Use label_text.
	(gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
	Look for an option by name before trying a binary search in
	doc_urls.
	(gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
	(gcc_urlifier::get_url_suffix_for_option): New.
	(make_gcc_urlifier): Add lang_mask param.
	(selftest::gcc_urlifier_cc_tests): Update for above changes.
	Verify that a URL is found for "-fpack-struct".
	* gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
	* gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
	* gcc.cc (driver::global_initializations): Pass 0 for lang_mask
	to make_gcc_urlifier.
	* opts-diagnostic.h (get_option_url): Add lang_mask param.
	* opts.cc (get_option_html_page): Remove special-casing for
	analyzer and LTO.
	(get_option_url_suffix): New.
	(get_option_url): Reimplement.
	(selftest::test_get_option_html_page): Rename to...
	(selftest::test_get_option_url_suffix): ...this and update for
	above changes.
	(selftest::opts_cc_tests): Update for renaming.
	* opts.h: Include "rich-location.h".
	(get_option_url_suffix): New decl.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* Makefile.in (ALL_OPT_URL_FILES): New.
	(GCC_OBJS): Add options-urls.o.
	(OBJS): Likewise.
	(OBJS-libcommon): Likewise.
	(s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
	inputs to opt-gather.awk.
	(options-urls.cc): New Makefile target.
	* opt-functions.awk (url_suffix): New function.
	(lang_url_suffix): New function.
	* options-urls-cc-gen.awk: New file.
	* opts.h (get_opt_url_suffix): New decl.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* params.opt.urls: New file, autogenerated by
	regenerate-opt-urls.py.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* common.opt.urls: New file, autogenerated by
	regenerate-opt-urls.py.
	* config/aarch64/aarch64.opt.urls: Likewise.
	* config/alpha/alpha.opt.urls: Likewise.
	* config/alpha/elf.opt.urls: Likewise.
	* config/arc/arc-tables.opt.urls: Likewise.
	* config/arc/arc.opt.urls: Likewise.
	* config/arm/arm-tables.opt.urls: Likewise.
	* config/arm/arm.opt.urls: Likewise.
	* config/arm/vxworks.opt.urls: Likewise.
	* config/avr/avr.opt.urls: Likewise.
	* config/bpf/bpf.opt.urls: Likewise.
	* config/c6x/c6x-tables.opt.urls: Likewise.
	* config/c6x/c6x.opt.urls: Likewise.
	* config/cris/cris.opt.urls: Likewise.
	* config/cris/elf.opt.urls: Likewise.
	* config/csky/csky.opt.urls: Likewise.
	* config/csky/csky_tables.opt.urls: Likewise.
	* config/darwin.opt.urls: Likewise.
	* config/dragonfly.opt.urls: Likewise.
	* config/epiphany/epiphany.opt.urls: Likewise.
	* config/fr30/fr30.opt.urls: Likewise.
	* config/freebsd.opt.urls: Likewise.
	* config/frv/frv.opt.urls: Likewise.
	* config/ft32/ft32.opt.urls: Likewise.
	* config/fused-madd.opt.urls: Likewise.
	* config/g.opt.urls: Likewise.
	* config/gcn/gcn.opt.urls: Likewise.
	* config/gnu-user.opt.urls: Likewise.
	* config/h8300/h8300.opt.urls: Likewise.
	* config/hpux11.opt.urls: Likewise.
	* config/i386/cygming.opt.urls: Likewise.
	* config/i386/cygwin.opt.urls: Likewise.
	* config/i386/djgpp.opt.urls: Likewise.
	* config/i386/i386.opt.urls: Likewise.
	* config/i386/mingw-w64.opt.urls: Likewise.
	* config/i386/mingw.opt.urls: Likewise.
	* config/i386/nto.opt.urls: Likewise.
	* config/ia64/ia64.opt.urls: Likewise.
	* config/ia64/ilp32.opt.urls: Likewise.
	* config/ia64/vms.opt.urls: Likewise.
	* config/iq2000/iq2000.opt.urls: Likewise.
	* config/linux-android.opt.urls: Likewise.
	* config/linux.opt.urls: Likewise.
	* config/lm32/lm32.opt.urls: Likewise.
	* config/loongarch/loongarch.opt.urls: Likewise.
	* config/lynx.opt.urls: Likewise.
	* config/m32c/m32c.opt.urls: Likewise.
	* config/m32r/m32r.opt.urls: Likewise.
	* config/m68k/ieee.opt.urls: Likewise.
	* config/m68k/m68k-tables.opt.urls: Likewise.
	* config/m68k/m68k.opt.urls: Likewise.
	* config/m68k/uclinux.opt.urls: Likewise.
	* config/mcore/mcore.opt.urls: Likewise.
	* config/microblaze/microblaze.opt.urls: Likewise.
	* config/mips/mips-tables.opt.urls: Likewise.
	* config/mips/mips.opt.urls: Likewise.
	* config/mips/sde.opt.urls: Likewise.
	* config/mmix/mmix.opt.urls: Likewise.
	* config/mn10300/mn10300.opt.urls: Likewise.
	* config/moxie/moxie.opt.urls: Likewise.
	* config/msp430/msp430.opt.urls: Likewise.
	* config/nds32/nds32-elf.opt.urls: Likewise.
	* config/nds32/nds32-linux.opt.urls: Likewise.
	* config/nds32/nds32.opt.urls: Likewise.
	* config/netbsd-elf.opt.urls: Likewise.
	* config/netbsd.opt.urls: Likewise.
	* config/nios2/elf.opt.urls: Likewise.
	* config/nios2/nios2.opt.urls: Likewise.
	* config/nvptx/nvptx-gen.opt.urls: Likewise.
	* config/nvptx/nvptx.opt.urls: Likewise.
	* config/openbsd.opt.urls: Likewise.
	* config/or1k/elf.opt.urls: Likewise.
	* config/or1k/or1k.opt.urls: Likewise.
	* config/pa/pa-hpux.opt.urls: Likewise.
	* config/pa/pa-hpux1010.opt.urls: Likewise.
	* config/pa/pa-hpux1111.opt.urls: Likewise.
	* config/pa/pa-hpux1131.opt.urls: Likewise.
	* config/pa/pa.opt.urls: Likewise.
	* config/pa/pa64-hpux.opt.urls: Likewise.
	* config/pdp11/pdp11.opt.urls: Likewise.
	* config/pru/pru.opt.urls: Likewise.
	* config/riscv/riscv.opt.urls: Likewise.
	* config/rl78/rl78.opt.urls: Likewise.
	* config/rpath.opt.urls: Likewise.
	* config/rs6000/476.opt.urls: Likewise.
	* config/rs6000/aix64.opt.urls: Likewise.
	* config/rs6000/darwin.opt.urls: Likewise.
	* config/rs6000/linux64.opt.urls: Likewise.
	* config/rs6000/rs6000-tables.opt.urls: Likewise.
	* config/rs6000/rs6000.opt.urls: Likewise.
	* config/rs6000/sysv4.opt.urls: Likewise.
	* config/rtems.opt.urls: Likewise.
	* config/rx/elf.opt.urls: Likewise.
	* config/rx/rx.opt.urls: Likewise.
	* config/s390/s390.opt.urls: Likewise.
	* config/s390/tpf.opt.urls: Likewise.
	* config/sh/sh.opt.urls: Likewise.
	* config/sh/superh.opt.urls: Likewise.
	* config/sol2.opt.urls: Likewise.
	* config/sparc/long-double-switch.opt.urls: Likewise.
	* config/sparc/sparc.opt.urls: Likewise.
	* config/stormy16/stormy16.opt.urls: Likewise.
	* config/v850/v850.opt.urls: Likewise.
	* config/vax/elf.opt.urls: Likewise.
	* config/vax/vax.opt.urls: Likewise.
	* config/visium/visium.opt.urls: Likewise.
	* config/vms/vms.opt.urls: Likewise.
	* config/vxworks-smp.opt.urls: Likewise.
	* config/vxworks.opt.urls: Likewise.
	* config/xtensa/elf.opt.urls: Likewise.
	* config/xtensa/uclinux.opt.urls: Likewise.
	* config/xtensa/xtensa.opt.urls: Likewise.
	* config/bfin/bfin.opt.urls: New file.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* Makefile.in (OPT_URLS_HTML_DEPS): New.
	(regenerate-opt-urls): New target.
	(regenerate-opt-urls-unit-test): New target.
	* doc/options.texi (Option properties): Add UrlSuffix and
	description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
	* doc/sourcebuild.texi (Anatomy of a Language Front End): Add
	reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
	and Makefile.in's OPT_URLS_HTML_DEPS.
	(Anatomy of a Target Back End): Add
	reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
	* regenerate-opt-urls.py: New file.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic-format-sarif.cc
	(sarif_builder::make_logical_location_object): Convert to...
	(make_sarif_logical_location_object): ...this.
	(sarif_builder::set_any_logical_locs_arr): Update for above
	change.
	(sarif_builder::make_thread_flow_location_object): Call
	maybe_add_sarif_properties on each diagnostic_event.
	* diagnostic-format-sarif.h (class logical_location): New forward
	decl.
	(make_sarif_logical_location_object): New decl.
	* diagnostic-path.h (class sarif_object): New forward decl.
	(diagnostic_event::maybe_add_sarif_properties): New vfunc.

2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
	    Patrick Lin  <patrick@andestech.com>
	    Rufus Chen  <rufus@andestech.com>
	    Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
	with Nan-boxing value.
	* config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.

2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
	    Jeff Law  <jlaw@ventanamicro.com>

	PR rtl-optimization/104914
	* expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
	a sign or zero extension is only required if the modified field
	overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
	targets, don't refer to the temporarily incorrectly extended value
	using a SUBREG, but instead generate an explicit TRUNCATE rtx.

2024-01-04  Pan Li  <pan2.li@intel.com>

	Revert:
	2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Kito Cheng  <kito.cheng@sifive.com>

	* config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
	offset of fcsr.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
	(compute_nregs_for_mode): Refine LMUL.
	(max_number_of_live_regs): Ditto.
	(compute_estimated_lmul): Ditto.
	(has_unexpected_spills_p): Ditto.

2024-01-04  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
	Remove useless forward declaration.
	(loongarch_is_even_extraction): Remove useless forward declaration.
	(loongarch_try_expand_lsx_vshuf_const): Removed.
	(loongarch_expand_vec_perm_const_1): Merged.
	(loongarch_is_double_duplicate): Removed.
	(loongarch_is_center_extraction): Ditto.
	(loongarch_is_reversing_permutation): Ditto.
	(loongarch_is_di_misalign_extract): Ditto.
	(loongarch_is_si_misalign_extract): Ditto.
	(loongarch_is_lasx_lowpart_extract): Ditto.
	(loongarch_is_op_reverse_perm): Ditto.
	(loongarch_is_single_op_perm): Ditto.
	(loongarch_is_divisible_perm): Ditto.
	(loongarch_is_triple_stride_extract): Ditto.
	(loongarch_expand_vec_perm_const_2): Merged.
	(loongarch_expand_vec_perm_const): New.
	(loongarch_vectorize_vec_perm_const): Adjust.

2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>

	* omp-general.cc: Fix comment typos and misplaced/confusing
	comments.  Delete redundant include of omp-general.h.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

	PR rtl-optimization/104914
	* config/mips/mips.md (insqisi_extended): New patterns.
	(inshisi_extended): Ditto.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.cc (mips_insn_cost): New function.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.md (perf_ratio): New attribute.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113206
	PR target/113209
	* config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
	(pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
	blocks belong to infinite loop.
	(pre_vsetvl::emit_vsetvl): Remove fake edges.
	* config/riscv/t-riscv: Add a new include file.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/vector.md: Fix indent.

2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>

	* tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
	OMP_CLAUSE__SIMDUID_.
	* tree.cc (omp_clause_num_ops): Update position of entry for
	OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
	(omp_clause_code_name): Likewise.

2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>

	* config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
	printing of FUNC_MAP/IND_FUNC_MAP labels.

2024-01-03  Jakub Jelinek  <jakub@redhat.com>

	* gcc.cc (process_command): Update copyright notice dates.
	* gcov-dump.cc (print_version): Ditto.
	* gcov.cc (print_version): Ditto.
	* gcov-tool.cc (print_version): Ditto.
	* gengtype.cc (create_file): Ditto.
	* doc/cpp.texi: Bump @copying's copyright year.
	* doc/cppinternals.texi: Ditto.
	* doc/gcc.texi: Ditto.
	* doc/gccint.texi: Ditto.
	* doc/gcov.texi: Ditto.
	* doc/install.texi: Ditto.
	* doc/invoke.texi: Ditto.

2024-01-03  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/simd.md (fmax<mode>3): New define_insn.
	(fmin<mode>3): Likewise.
	(reduc_fmax_scal_<mode>3): New define_expand.
	(reduc_fmin_scal_<mode>3): Likewise.

2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113112
	* config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
	(max_number_of_live_regs): Ditto.
	(has_unexpected_spills_p): Ditto.

2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/vector.md:
	Use vector_length_operand for vsetvl patterns.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
	(expand_cond_len_op): Add simplification of dummy len and dummy mask.

2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>

	* config/aarch64/aarch64-tuning-flags.def
	(AARCH64_EXTRA_TUNING_OPTION): New tuning option
	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
	* config/aarch64/aarch64.cc
	(aarch64_override_options_internal): Set
	param_fully_pipelined_fma according to tuning option.
	* config/aarch64/tuning_models/ampere1.h: Add
	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
	* config/aarch64/tuning_models/ampere1a.h: Likewise.
	* config/aarch64/tuning_models/ampere1b.h: Likewise.

2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/vector-crypto.md: Modify copyright year.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.

2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config.in: Regenerate.
	* config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
	* config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
	Added TLS Le Relax support.
	(loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
	* config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
	* configure: Regenerate.
	* configure.ac: Check if binutils supports TLS le relax.

2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/iterators.md: Add rotate insn name.
	* config/riscv/riscv.md: Add new insns name for crypto vector.
	* config/riscv/vector-iterators.md: Add new iterators for crypto vector.
	* config/riscv/vector.md: Add the corresponding attr for crypto vector.
	* config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113112
	* config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
	pointer type liveness count.

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are permitted in any medium without royalty provided the copyright
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