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Low-level accessors
bladeRF1-specific API

## Description

In a most cases, higher-level routines should be used. These routines are only intended to support development and testing.

Use these routines with great care, and be sure to reference the relevant schematics, data sheets, and source code (i.e., firmware and hdl).

Be careful when mixing these calls with higher-level routines that manipulate the same registers/settings.

These functions are thread-safe.

## Data Structures

struct | bladerf_lms_dc_cals

## Macros

#define | BLADERF_GPIO_LMS_RX_ENABLE (1 << 1)
#define | BLADERF_GPIO_LMS_TX_ENABLE (1 << 2)
#define | BLADERF_GPIO_TX_LB_ENABLE (2 << 3)
#define | BLADERF_GPIO_TX_HB_ENABLE (1 << 3)
#define | BLADERF_GPIO_COUNTER_ENABLE (1 << 9)
#define | BLADERF_GPIO_RX_MUX_MASK (0x7 << BLADERF_GPIO_RX_MUX_SHIFT)
#define | BLADERF_GPIO_RX_MUX_SHIFT 8
#define | BLADERF_GPIO_RX_LB_ENABLE (2 << 5)
#define | BLADERF_GPIO_RX_HB_ENABLE (1 << 5)
#define | BLADERF_GPIO_FEATURE_SMALL_DMA_XFER (1 << 7)
#define | BLADERF_GPIO_PACKET (1 << 19)
#define | BLADERF_GPIO_8BIT_MODE (1 << 20)
#define | BLADERF_GPIO_AGC_ENABLE (1 << 18)
#define | BLADERF_GPIO_TIMESTAMP (1 << 16)
#define | BLADERF_GPIO_TIMESTAMP_DIV2 (1 << 17)
#define | BLADERF_GPIO_PACKET_CORE_PRESENT (1 << 28)

## Functions

API_EXPORT int CALL_CONV | bladerf_dac_write (struct bladerf *dev, uint16_t val)
API_EXPORT int CALL_CONV | bladerf_dac_read (struct bladerf *dev, uint16_t *val)
API_EXPORT int CALL_CONV | bladerf_si5338_read (struct bladerf *dev, uint8_t address, uint8_t *val)
API_EXPORT int CALL_CONV | bladerf_si5338_write (struct bladerf *dev, uint8_t address, uint8_t val)
API_EXPORT int CALL_CONV | bladerf_lms_read (struct bladerf *dev, uint8_t address, uint8_t *val)
API_EXPORT int CALL_CONV | bladerf_lms_write (struct bladerf *dev, uint8_t address, uint8_t val)
API_EXPORT int CALL_CONV | bladerf_lms_set_dc_cals (struct bladerf *dev, const struct bladerf_lms_dc_cals *dc_cals)
API_EXPORT int CALL_CONV | bladerf_lms_get_dc_cals (struct bladerf *dev, struct bladerf_lms_dc_cals *dc_cals)
API_EXPORT int CALL_CONV | bladerf_xb_spi_write (struct bladerf *dev, uint32_t val)

## Macro Definition Documentation

## BLADERF_GPIO_8BIT_MODE

#define BLADERF_GPIO_8BIT_MODE (1 << 20)

Enable 8bit sample mode

Definition at line 1377 of file bladeRF1.h.

## BLADERF_GPIO_AGC_ENABLE

#define BLADERF_GPIO_AGC_ENABLE (1 << 18)

AGC enable control bit

Note
  This is set using bladerf_set_gain_mode().

Definition at line 1384 of file bladeRF1.h.

## BLADERF_GPIO_COUNTER_ENABLE

#define BLADERF_GPIO_COUNTER_ENABLE (1 << 9)

Counter mode enable

Setting this bit to 1 instructs the FPGA to replace the (I, Q) pair in sample data with an incrementing, little-endian, 32-bit counter value. A 0 in bit specifies that sample data should be sent (as normally done).

This feature is useful when debugging issues involving dropped samples.

Definition at line 1330 of file bladeRF1.h.

## BLADERF_GPIO_FEATURE_SMALL_DMA_XFER

#define BLADERF_GPIO_FEATURE_SMALL_DMA_XFER (1 << 7)

This GPIO bit configures the FPGA to use smaller DMA transfers (256 cycles instead of 512). This is required when the device is not connected at Super Speed (i.e., when it is connected at High Speed).

However, the caller need not set this in bladerf_config_gpio_write() calls. The library will set this as needed; callers generally do not need to be concerned with setting/clearing this bit.

Definition at line 1367 of file bladeRF1.h.

## BLADERF_GPIO_LMS_RX_ENABLE

#define BLADERF_GPIO_LMS_RX_ENABLE (1 << 1)

Enable LMS receive

Note
  This bit is set/cleared by bladerf_enable_module()

Definition at line 1298 of file bladeRF1.h.

## BLADERF_GPIO_LMS_TX_ENABLE

#define BLADERF_GPIO_LMS_TX_ENABLE (1 << 2)

Enable LMS transmit

Note
  This bit is set/cleared by bladerf_enable_module()

Definition at line 1305 of file bladeRF1.h.

## BLADERF_GPIO_PACKET

#define BLADERF_GPIO_PACKET (1 << 19)

Enable Packet mode

Definition at line 1372 of file bladeRF1.h.

## BLADERF_GPIO_PACKET_CORE_PRESENT

#define BLADERF_GPIO_PACKET_CORE_PRESENT (1 << 28)

Packet capable core present bit.

Note
  This is a read-only bit. The FPGA sets its value, and uses it to inform host that there is a core capable of using packets in the FPGA.

Definition at line 1414 of file bladeRF1.h.

## BLADERF_GPIO_RX_HB_ENABLE

#define BLADERF_GPIO_RX_HB_ENABLE (1 << 5)

Switch to use RX high band (1.5GHz - 3.8GHz)

Note
  This is set using bladerf_set_frequency().

Definition at line 1356 of file bladeRF1.h.

## BLADERF_GPIO_RX_LB_ENABLE

#define BLADERF_GPIO_RX_LB_ENABLE (2 << 5)

Switch to use RX low band (300M - 1.5GHz)

Note
  This is set using bladerf_set_frequency().

Definition at line 1349 of file bladeRF1.h.

## BLADERF_GPIO_RX_MUX_MASK

#define BLADERF_GPIO_RX_MUX_MASK (0x7 << BLADERF_GPIO_RX_MUX_SHIFT)

Bit mask representing the rx mux selection

Note
  These bits are set using bladerf_set_rx_mux()

Definition at line 1337 of file bladeRF1.h.

## BLADERF_GPIO_RX_MUX_SHIFT

#define BLADERF_GPIO_RX_MUX_SHIFT 8

Starting bit index of the RX mux values in FX3 <-> FPGA GPIO bank

Definition at line 1342 of file bladeRF1.h.

## BLADERF_GPIO_TIMESTAMP

#define BLADERF_GPIO_TIMESTAMP (1 << 16)

Enable-bit for timestamp counter in the FPGA

Definition at line 1389 of file bladeRF1.h.

## BLADERF_GPIO_TIMESTAMP_DIV2

#define BLADERF_GPIO_TIMESTAMP_DIV2 (1 << 17)

Timestamp 2x divider control.

Note
  Important: This bit has no effect and is always enabled (1) in FPGA versions >= v0.3.0.
  The remainder of the description of this bit is presented here for historical purposes only. It is only relevant to FPGA versions <= v0.1.2.

By default (value = 0), the sample counter is incremented with I and Q, yielding two counts per sample.

Set this bit to 1 to enable a 2x timestamp divider, effectively achieving 1 timestamp count per sample.

Definition at line 1406 of file bladeRF1.h.

## BLADERF_GPIO_TX_HB_ENABLE

#define BLADERF_GPIO_TX_HB_ENABLE (1 << 3)

Switch to use TX high band (1.5GHz - 3.8GHz)

Note
  This is set using bladerf_set_frequency().

Definition at line 1319 of file bladeRF1.h.

## BLADERF_GPIO_TX_LB_ENABLE

#define BLADERF_GPIO_TX_LB_ENABLE (2 << 3)

Switch to use TX low band (300MHz - 1.5GHz)

Note
  This is set using bladerf_set_frequency().

Definition at line 1312 of file bladeRF1.h.

## Function Documentation

## bladerf_dac_read()

API_EXPORT int CALL_CONV bladerf_dac_read | ( | struct bladerf * | dev,
|  | uint16_t * | val )

Read value from VCTCXO trim DAC.

Deprecated
  Use bladerf_trim_dac_read().

This is similar to bladerf_get_vctcxo_trim(), except that it returns the current trim DAC value, as opposed to the calibration value read from flash.

Use this if you are trying to query the value after having previously made calls to bladerf_dac_write().

Parameters

  | dev | Device handle
  [out] | val | Value to read from VCTCXO trim DAC

Returns
  0 on success, value from Error codes list on failure

## bladerf_dac_write()

API_EXPORT int CALL_CONV bladerf_dac_write | ( | struct bladerf * | dev,
|  | uint16_t | val )

Write value to VCTCXO trim DAC.

Deprecated
  Use bladerf_trim_dac_write().

This should not be used when the VCTCXO tamer is enabled.

Parameters

  | dev | Device handle
  [in] | val | Value to write to VCTCXO trim DAC

Returns
  0 on success, value from Error codes list on failure

## bladerf_lms_get_dc_cals()

API_EXPORT int CALL_CONV bladerf_lms_get_dc_cals | ( | struct bladerf * | dev,
|  | struct bladerf_lms_dc_cals * | dc_cals )

Retrieve the current DC calibration values from the LMS6002

Parameters

  | dev | Device handle
  [out] | dc_cals | Populated with current values

Returns
  0 on success, value from Error codes list on failure

## bladerf_lms_read()

API_EXPORT int CALL_CONV bladerf_lms_read | ( | struct bladerf * | dev,
|  | uint8_t | address,
|  | uint8_t * | val )

Read a LMS register

Parameters

  | dev | Device handle
  [in] | address | LMS register address
  [out] | val | Register value

Returns
  0 on success, value from Error codes list on failure

## bladerf_lms_set_dc_cals()

API_EXPORT int CALL_CONV bladerf_lms_set_dc_cals | ( | struct bladerf * | dev,
|  | const struct bladerf_lms_dc_cals * | dc_cals )

Manually load values into LMS6002 DC calibration registers.

This is generally intended for applying a set of known values resulting from a previous run of the LMS autocalibrations.

Parameters

  | dev | Device handle
  [in] | dc_cals | Calibration values to load. Values set to <0 will not be applied.

Returns
  0 on success, value from Error codes list on failure

## bladerf_lms_write()

API_EXPORT int CALL_CONV bladerf_lms_write | ( | struct bladerf * | dev,
|  | uint8_t | address,
|  | uint8_t | val )

Write a LMS register

Parameters

  | dev | Device handle
  [in] | address | LMS register address
  [in] | val | Value to write to register

Returns
  0 on success, value from Error codes list on failure

## bladerf_si5338_read()

API_EXPORT int CALL_CONV bladerf_si5338_read | ( | struct bladerf * | dev,
|  | uint8_t | address,
|  | uint8_t * | val )

Read a Si5338 register

Parameters

  | dev | Device handle
  [in] | address | Si5338 register address
  [out] | val | Register value

Returns
  0 on success, value from Error codes list on failure

## bladerf_si5338_write()

API_EXPORT int CALL_CONV bladerf_si5338_write | ( | struct bladerf * | dev,
|  | uint8_t | address,
|  | uint8_t | val )

Write a Si5338 register

Parameters

  | dev | Device handle
  [in] | address | Si5338 register address
  [in] | val | Value to write to register

Returns
  0 on success, value from Error codes list on failure

## bladerf_xb_spi_write()

API_EXPORT int CALL_CONV bladerf_xb_spi_write | ( | struct bladerf * | dev,
|  | uint32_t | val )

Write value to secondary XB SPI

Parameters

  | dev | Device handle
  [out] | val | Value to write to XB SPI

Returns
  0 on success, value from Error codes list on failure